178 lines
3.6 KiB
C
178 lines
3.6 KiB
C
#include "global.h"
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#define REG_BUFFER_SIZE 0x60
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#define REG_BUFFER(offset) (*(u16 *)(&gGpuRegBuffer[offset]))
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#define GPU_REG(offset) (*(vu16 *)(REG_BASE + offset))
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#define EMPTY_SLOT 0xFF
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extern u8 gGpuRegBuffer[REG_BUFFER_SIZE];
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extern u8 gGpuRegWaitingList[REG_BUFFER_SIZE];
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extern bool8 gGpuRegBufferLocked;
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extern bool8 gShouldSyncRegIE;
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extern u16 gRegIE;
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static void CopyBufferedValueToGpuReg(u8 regOffset);
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static void SyncRegIE();
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static void UpdateRegDispstatIntrBits(u16 regIE);
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void InitGpuRegManager()
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{
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s32 i;
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for (i = 0; i < REG_BUFFER_SIZE; i++) {
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gGpuRegBuffer[i] = 0;
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gGpuRegWaitingList[i] = EMPTY_SLOT;
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}
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gGpuRegBufferLocked = FALSE;
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gShouldSyncRegIE = FALSE;
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gRegIE = 0;
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}
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static void CopyBufferedValueToGpuReg(u8 regOffset)
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{
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if (regOffset == REG_OFFSET_DISPSTAT) {
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REG_DISPSTAT &= ~(DISPSTAT_HBLANK_INTR | DISPSTAT_VBLANK_INTR);
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REG_DISPSTAT |= REG_BUFFER(REG_OFFSET_DISPSTAT);
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} else {
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GPU_REG(regOffset) = REG_BUFFER(regOffset);
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}
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}
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void CopyBufferedValuesToGpuRegs()
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{
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if (!gGpuRegBufferLocked) {
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s32 i;
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for (i = 0; i < REG_BUFFER_SIZE; i++) {
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u8 regOffset = gGpuRegWaitingList[i];
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if (regOffset == EMPTY_SLOT)
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return;
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CopyBufferedValueToGpuReg(regOffset);
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gGpuRegWaitingList[i] = EMPTY_SLOT;
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}
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}
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}
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void SetGpuReg(u8 regOffset, u16 value)
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{
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if (regOffset < REG_BUFFER_SIZE)
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{
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u16 vcount;
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REG_BUFFER(regOffset) = value;
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vcount = REG_VCOUNT;
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if ((vcount >= 161 && vcount <= 225)
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|| (REG_DISPCNT & DISPCNT_FORCED_BLANK)) {
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CopyBufferedValueToGpuReg(regOffset);
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} else {
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s32 i;
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gGpuRegBufferLocked = TRUE;
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for (i = 0; i < REG_BUFFER_SIZE && gGpuRegWaitingList[i] != EMPTY_SLOT; i++) {
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if (gGpuRegWaitingList[i] == regOffset) {
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gGpuRegBufferLocked = FALSE;
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return;
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}
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}
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gGpuRegWaitingList[i] = regOffset;
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gGpuRegBufferLocked = FALSE;
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}
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}
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}
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void SetGpuReg_ForcedBlank(u8 regOffset, u16 value)
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{
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if (regOffset < REG_BUFFER_SIZE)
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{
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REG_BUFFER(regOffset) = value;
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if (REG_DISPCNT & DISPCNT_FORCED_BLANK) {
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CopyBufferedValueToGpuReg(regOffset);
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} else {
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s32 i;
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gGpuRegBufferLocked = TRUE;
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for (i = 0; i < REG_BUFFER_SIZE && gGpuRegWaitingList[i] != EMPTY_SLOT; i++) {
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if (gGpuRegWaitingList[i] == regOffset) {
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gGpuRegBufferLocked = FALSE;
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return;
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}
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}
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gGpuRegWaitingList[i] = regOffset;
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gGpuRegBufferLocked = FALSE;
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}
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}
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}
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u16 GetGpuReg(u8 regOffset)
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{
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if (regOffset == REG_OFFSET_DISPSTAT)
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return REG_DISPSTAT;
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if (regOffset == REG_OFFSET_VCOUNT)
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return REG_VCOUNT;
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return REG_BUFFER(regOffset);
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}
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void SetGpuRegBits(u8 regOffset, u16 mask)
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{
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u16 regValue = REG_BUFFER(regOffset);
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SetGpuReg(regOffset, regValue | mask);
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}
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void ClearGpuRegBits(u8 regOffset, u16 mask)
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{
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u16 regValue = REG_BUFFER(regOffset);
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SetGpuReg(regOffset, regValue & ~mask);
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}
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static void SyncRegIE()
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{
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if (gShouldSyncRegIE) {
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u16 temp = REG_IME;
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REG_IME = 0;
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REG_IE = gRegIE;
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REG_IME = temp;
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gShouldSyncRegIE = FALSE;
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}
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}
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void EnableInterrupts(u16 mask)
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{
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gRegIE |= mask;
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gShouldSyncRegIE = TRUE;
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SyncRegIE();
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UpdateRegDispstatIntrBits(gRegIE);
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}
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void DisableInterrupts(u16 mask)
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{
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gRegIE &= ~mask;
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gShouldSyncRegIE = TRUE;
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SyncRegIE();
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UpdateRegDispstatIntrBits(gRegIE);
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}
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static void UpdateRegDispstatIntrBits(u16 regIE)
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{
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u16 oldValue = GetGpuReg(REG_OFFSET_DISPSTAT) & (DISPSTAT_HBLANK_INTR | DISPSTAT_VBLANK_INTR);
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u16 newValue = 0;
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if (regIE & INTR_FLAG_VBLANK)
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newValue |= DISPSTAT_VBLANK_INTR;
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if (regIE & INTR_FLAG_HBLANK)
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newValue |= DISPSTAT_HBLANK_INTR;
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if (oldValue != newValue)
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SetGpuReg(REG_OFFSET_DISPSTAT, newValue);
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}
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