armwrestler-fix: Properly handle misaligned addresses LDR/LDRH/LDRSH
Former-commit-id: 742a7c2b8413fa9d45df1575a0b14b8d1ab697c4
This commit is contained in:
Michel Heily
parent
2a66e525b1
commit
009e46f6d5
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@ -98,11 +98,12 @@ impl BarrelShifterValue {
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impl Core {
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/// Performs a generic barrel shifter operation
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fn barrel_shift(
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pub fn barrel_shift(
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&mut self,
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val: i32,
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amount: u32,
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shift: BarrelShiftOpCode,
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carry: &mut bool,
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immediate: bool,
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) -> i32 {
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//
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@ -128,33 +129,33 @@ impl Core {
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BarrelShiftOpCode::LSL => match amount {
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0 => val,
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x if x < 32 => {
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self.cpsr.set_C(val.wrapping_shr(32 - x) & 1 == 1);
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*carry = val.wrapping_shr(32 - x) & 1 == 1;
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val << x
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}
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32 => {
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self.cpsr.set_C(val & 1 == 1);
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*carry = val & 1 == 1;
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0
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}
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_ => {
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self.cpsr.set_C(false);
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*carry = false;
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0
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}
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},
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BarrelShiftOpCode::LSR => match amount {
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0 | 32 => {
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if immediate {
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self.cpsr.set_C((val as u32).bit(31));
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*carry = (val as u32).bit(31);
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0
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} else {
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val
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}
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}
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x if x < 32 => {
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self.cpsr.set_C(val >> (amount - 1) & 1 == 1);
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*carry = val >> (amount - 1) & 1 == 1;
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((val as u32) >> amount) as i32
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}
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_ => {
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self.cpsr.set_C(false);
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*carry = false;
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0
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}
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},
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@ -162,7 +163,7 @@ impl Core {
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0 => {
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if immediate {
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let bit31 = (val as u32).bit(31);
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self.cpsr.set_C(bit31);
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*carry = bit31;
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if bit31 {
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-1
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} else {
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@ -173,12 +174,12 @@ impl Core {
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}
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}
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x if x < 32 => {
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self.cpsr.set_C(val.wrapping_shr(amount - 1) & 1 == 1);
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*carry = val.wrapping_shr(amount - 1) & 1 == 1;
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val.wrapping_shr(amount)
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}
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_ => {
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let bit31 = (val as u32).bit(31);
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self.cpsr.set_C(bit31);
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*carry = bit31;
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if bit31 {
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-1
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} else {
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@ -192,7 +193,7 @@ impl Core {
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if immediate {
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/* RRX */
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let old_c = self.cpsr.C() as i32;
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self.cpsr.set_C(val & 0b1 != 0);
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*carry = val & 0b1 != 0;
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((val as u32) >> 1) as i32 | (old_c << 31)
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} else {
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val
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@ -205,7 +206,7 @@ impl Core {
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} else {
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val
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};
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self.cpsr.set_C((val as u32).bit(31));
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*carry = (val as u32).bit(31);
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val
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}
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}
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@ -215,13 +216,19 @@ impl Core {
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pub fn register_shift(&mut self, reg: usize, shift: ShiftedRegister) -> CpuResult<i32> {
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let val = self.get_reg(reg) as i32;
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let mut carry = self.cpsr.C();
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match shift {
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ShiftedRegister::ByAmount(amount, shift) => {
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Ok(self.barrel_shift(val, amount, shift, true))
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let result = self.barrel_shift(val, amount, shift, &mut carry, true);
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self.cpsr.set_C(carry);
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Ok(result)
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}
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ShiftedRegister::ByRegister(reg, shift) => {
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if reg != REG_PC {
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Ok(self.barrel_shift(val, self.get_reg(reg) & 0xff, shift, false))
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let result =
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self.barrel_shift(val, self.get_reg(reg) & 0xff, shift, &mut carry, false);
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self.cpsr.set_C(carry);
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Ok(result)
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} else {
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Err(CpuError::IllegalInstruction)
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}
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@ -232,7 +232,7 @@ impl Core {
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let data = if insn.transfer_size() == 1 {
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self.load_8(addr, bus) as u32
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} else {
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self.load_32(addr, bus)
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self.ldr_word(addr, bus)
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};
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self.set_reg(insn.rd(), data);
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@ -287,10 +287,8 @@ impl Core {
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if insn.load_flag() {
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let data = match insn.halfword_data_transfer_type().unwrap() {
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ArmHalfwordTransferType::SignedByte => self.load_8(addr, bus) as u8 as i8 as u32,
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ArmHalfwordTransferType::SignedHalfwords => {
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self.load_16(addr, bus) as u16 as i16 as u32
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}
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ArmHalfwordTransferType::UnsignedHalfwords => self.load_16(addr, bus) as u16 as u32,
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ArmHalfwordTransferType::SignedHalfwords => self.ldr_sign_half(addr, bus),
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ArmHalfwordTransferType::UnsignedHalfwords => self.ldr_half(addr, bus),
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};
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self.set_reg(insn.rd(), data);
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@ -5,6 +5,7 @@ use num_traits::Num;
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pub use super::exception::Exception;
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use super::{
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alu::*,
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arm::*,
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bus::{Bus, MemoryAccess, MemoryAccessType, MemoryAccessType::*, MemoryAccessWidth::*},
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psr::RegPSR,
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@ -75,7 +76,7 @@ impl Core {
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match r {
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0...14 => self.gpr[r],
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15 => self.pc,
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_ => panic!("invalid register"),
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_ => panic!("invalid register {}", r),
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}
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}
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@ -123,6 +124,48 @@ impl Core {
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}
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}
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pub fn ror(&mut self, value: u32, rotation: u32) -> u32 {
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let mut carry = false; // we don't need to update the carry flag
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self.barrel_shift(
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value as i32,
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rotation,
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BarrelShiftOpCode::ROR,
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&mut carry,
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false,
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) as u32
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}
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/// Helper function for "ldr" instruction that handles misaligned addresses
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pub fn ldr_word(&mut self, addr: Addr, bus: &Bus) -> u32 {
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if addr & 0x3 != 0 {
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let rotation = (addr & 0x3) << 3;
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let value = self.load_32(addr & !0x3, bus);
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self.ror(value, rotation)
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} else {
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self.load_32(addr, bus)
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}
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}
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/// Helper function for "ldrh" instruction that handles misaligned addresses
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pub fn ldr_half(&mut self, addr: Addr, bus: &Bus) -> u32 {
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if addr & 0x1 != 0 {
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let rotation = (addr & 0x1) << 3;
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let value = self.load_16(addr & !0x1, bus);
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self.ror(value as u32, rotation)
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} else {
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self.load_16(addr, bus) as u32
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}
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}
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/// Helper function for "ldrsh" instruction that handles misaligned addresses
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pub fn ldr_sign_half(&mut self, addr: Addr, bus: &Bus) -> u32 {
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if addr & 0x1 != 0 {
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self.load_8(addr, bus) as i8 as i32 as u32
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} else {
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self.load_16(addr, bus) as i16 as i32 as u32
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}
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}
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pub fn get_registers(&self) -> [u32; 15] {
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self.gpr.clone()
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}
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@ -211,20 +254,20 @@ impl Core {
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}
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}
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pub fn load_32(&mut self, addr: Addr, bus: &mut Bus) -> u32 {
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pub fn load_32(&mut self, addr: Addr, bus: &Bus) -> u32 {
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self.add_cycles(addr, bus, self.cycle_type(addr) + MemoryAccess32);
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self.memreq = addr;
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bus.read_32(addr)
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}
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pub fn load_16(&mut self, addr: Addr, bus: &mut Bus) -> u16 {
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pub fn load_16(&mut self, addr: Addr, bus: &Bus) -> u16 {
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let cycle_type = self.cycle_type(addr);
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self.add_cycles(addr, bus, cycle_type + MemoryAccess16);
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self.memreq = addr;
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bus.read_16(addr)
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}
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pub fn load_8(&mut self, addr: Addr, bus: &mut Bus) -> u8 {
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pub fn load_8(&mut self, addr: Addr, bus: &Bus) -> u8 {
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let cycle_type = self.cycle_type(addr);
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self.add_cycles(addr, bus, cycle_type + MemoryAccess8);
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self.memreq = addr;
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@ -169,7 +169,7 @@ impl Core {
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let data = if insn.is_transferring_bytes() {
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self.load_8(addr, bus) as u32
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} else {
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self.load_32(addr, bus)
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self.ldr_word(addr, bus)
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};
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self.set_reg(insn.rd(), data);
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@ -216,7 +216,7 @@ impl Core {
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(false, true) =>
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/* ldrh */
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{
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self.gpr[rd] = self.load_16(addr, bus) as u32
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self.gpr[rd] = self.ldr_half(addr, bus)
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}
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(true, false) =>
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/* ldsb */
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@ -227,7 +227,7 @@ impl Core {
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(true, true) =>
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/* ldsh */
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{
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let val = self.load_16(addr, bus) as i16 as i32 as u32;
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let val = self.ldr_sign_half(addr, bus);
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self.gpr[rd] = val;
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}
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}
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@ -257,7 +257,7 @@ impl Core {
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let base = self.gpr[insn.rb()] as i32;
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let addr = base.wrapping_add((insn.offset5() << 1) as i32) as Addr;
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if insn.is_load() {
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let data = self.load_16(addr, bus);
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let data = self.ldr_half(addr, bus);
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self.add_cycle();
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self.gpr[insn.rd()] = data as u32;
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} else {
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