core: Get rid of that BoxedMemory nonsense

Just directly impl Bus trait for Box<[u8]>


Former-commit-id: 7b8a29972520afb7ff197708b9c2146b293a5f29
Former-commit-id: 0c528165ed899fad14b1e25995fdfe8ae004da2a
This commit is contained in:
Michel Heily 2020-10-17 16:58:52 -07:00
parent 130a7608e7
commit 1ca261e5c7
7 changed files with 56 additions and 75 deletions

View file

@ -62,3 +62,26 @@ pub trait DebugRead: Bus {
bytes bytes
} }
} }
/// The caller is assumed to handle out of bound accesses,
/// For performance reasons, this impl trusts that 'addr' is within the array range.
impl Bus for Box<[u8]> {
#[inline]
fn read_8(&mut self, addr: Addr) -> u8 {
unsafe { *self.get_unchecked(addr as usize) }
}
#[inline]
fn write_8(&mut self, addr: Addr, value: u8) {
unsafe {
*self.get_unchecked_mut(addr as usize) = value;
}
}
}
impl DebugRead for Box<[u8]> {
#[inline]
fn debug_read_8(&mut self, addr: Addr) -> u8 {
self[addr as usize]
}
}

View file

@ -261,7 +261,7 @@ impl Debugger {
let save = read_bin_file(&Path::new(&load_path)) let save = read_bin_file(&Path::new(&load_path))
.expect("failed to read save state from file"); .expect("failed to read save state from file");
self.gba self.gba
.restore_state(&save, Box::from(self.gba.sysbus.get_bios())) .restore_state(&save)
.expect("failed to deserialize"); .expect("failed to deserialize");
} }
ListSymbols(Some(pattern)) => { ListSymbols(Some(pattern)) => {

View file

@ -179,7 +179,7 @@ impl GameBoyAdvance {
bincode::serialize(&s) bincode::serialize(&s)
} }
pub fn restore_state(&mut self, bytes: &[u8], bios: Box<[u8]>) -> bincode::Result<()> { pub fn restore_state(&mut self, bytes: &[u8]) -> bincode::Result<()> {
let decoded: Box<SaveState> = bincode::deserialize_from(bytes)?; let decoded: Box<SaveState> = bincode::deserialize_from(bytes)?;
self.cpu.restore_state(decoded.cpu_state); self.cpu.restore_state(decoded.cpu_state);
@ -188,7 +188,6 @@ impl GameBoyAdvance {
self.io_devs = Shared::new(decoded.io_devs); self.io_devs = Shared::new(decoded.io_devs);
// Restore memory state // Restore memory state
self.cpu.set_memory_interface(self.sysbus.clone()); self.cpu.set_memory_interface(self.sysbus.clone());
self.sysbus.set_bios(bios);
self.sysbus.set_iwram(decoded.iwram); self.sysbus.set_iwram(decoded.iwram);
self.sysbus.set_ewram(decoded.ewram); self.sysbus.set_ewram(decoded.ewram);
// Redistribute shared pointers // Redistribute shared pointers

View file

@ -11,7 +11,6 @@ use super::dma::{DmaNotifer, TIMING_HBLANK, TIMING_VBLANK};
use super::interrupt::{self, Interrupt, InterruptConnect, SharedInterruptFlags}; use super::interrupt::{self, Interrupt, InterruptConnect, SharedInterruptFlags};
use super::sched::*; use super::sched::*;
pub use super::sysbus::consts::*; pub use super::sysbus::consts::*;
use super::util::BoxedMemory;
#[cfg(not(feature = "no_video_interface"))] #[cfg(not(feature = "no_video_interface"))]
use super::VideoInterface; use super::VideoInterface;
@ -210,9 +209,9 @@ pub struct Gpu {
pub bldalpha: BlendAlpha, pub bldalpha: BlendAlpha,
pub bldy: u16, pub bldy: u16,
pub palette_ram: BoxedMemory, pub palette_ram: Box<[u8]>,
pub vram: BoxedMemory, pub vram: Box<[u8]>,
pub oam: BoxedMemory, pub oam: Box<[u8]>,
pub(super) vram_obj_tiles_start: u32, pub(super) vram_obj_tiles_start: u32,
@ -259,9 +258,9 @@ impl Gpu {
vcount: 0, vcount: 0,
cycles_left_for_current_state: CYCLES_HDRAW, cycles_left_for_current_state: CYCLES_HDRAW,
palette_ram: BoxedMemory::new(vec![0; PALETTE_RAM_SIZE].into_boxed_slice()), palette_ram: vec![0; PALETTE_RAM_SIZE].into_boxed_slice(),
vram: BoxedMemory::new(vec![0; VIDEO_RAM_SIZE].into_boxed_slice()), vram: vec![0; VIDEO_RAM_SIZE].into_boxed_slice(),
oam: BoxedMemory::new(vec![0; OAM_SIZE].into_boxed_slice()), oam: vec![0; OAM_SIZE].into_boxed_slice(),
obj_buffer: vec![Default::default(); DISPLAY_WIDTH * DISPLAY_HEIGHT], obj_buffer: vec![Default::default(); DISPLAY_WIDTH * DISPLAY_HEIGHT],

View file

@ -6,7 +6,7 @@ use super::cartridge::Cartridge;
use super::dma::DmaNotifer; use super::dma::DmaNotifer;
use super::iodev::{IoDevices, WaitControl}; use super::iodev::{IoDevices, WaitControl};
use super::sched::Scheduler; use super::sched::Scheduler;
use super::util::{BoxedMemory, Shared, WeakPointer}; use super::util::{Shared, WeakPointer};
pub mod consts { pub mod consts {
pub const WORK_RAM_SIZE: usize = 256 * 1024; pub const WORK_RAM_SIZE: usize = 256 * 1024;
@ -144,8 +144,8 @@ pub struct SysBus {
scheduler: Shared<Scheduler>, scheduler: Shared<Scheduler>,
bios: BoxedMemory, bios: BoxedMemory,
onboard_work_ram: BoxedMemory, ewram: Box<[u8]>,
internal_work_ram: BoxedMemory, iwram: Box<[u8]>,
pub cartridge: Cartridge, pub cartridge: Cartridge,
cycle_luts: CycleLookupTables, cycle_luts: CycleLookupTables,
@ -173,9 +173,9 @@ impl SysBus {
scheduler, scheduler,
cartridge, cartridge,
bios: BoxedMemory::new(bios_rom), bios: bios_rom,
onboard_work_ram: BoxedMemory::new(ewram), ewram,
internal_work_ram: BoxedMemory::new(iwram), iwram,
cycle_luts: luts, cycle_luts: luts,
trace_access: false, trace_access: false,
} }
@ -192,28 +192,20 @@ impl SysBus {
SysBus::new_with_memories(scheduler, io, cartridge, bios_rom, ewram, iwram) SysBus::new_with_memories(scheduler, io, cartridge, bios_rom, ewram, iwram)
} }
pub fn set_bios(&mut self, buffer: Box<[u8]>) {
self.bios.mem = buffer;
}
pub fn set_ewram(&mut self, buffer: Box<[u8]>) { pub fn set_ewram(&mut self, buffer: Box<[u8]>) {
self.onboard_work_ram.mem = buffer; self.ewram = buffer;
} }
pub fn set_iwram(&mut self, buffer: Box<[u8]>) { pub fn set_iwram(&mut self, buffer: Box<[u8]>) {
self.internal_work_ram.mem = buffer; self.iwram = buffer;
}
pub fn get_bios(&self) -> &[u8] {
&self.bios.mem
} }
pub fn get_ewram(&self) -> &[u8] { pub fn get_ewram(&self) -> &[u8] {
&self.onboard_work_ram.mem &self.ewram
} }
pub fn get_iwram(&self) -> &[u8] { pub fn get_iwram(&self) -> &[u8] {
&self.internal_work_ram.mem &self.iwram
} }
pub fn set_scheduler(&mut self, s: Shared<Scheduler>) { pub fn set_scheduler(&mut self, s: Shared<Scheduler>) {
@ -270,8 +262,8 @@ impl Bus for SysBus {
fn read_32(&mut self, addr: Addr) -> u32 { fn read_32(&mut self, addr: Addr) -> u32 {
match addr & 0xff000000 { match addr & 0xff000000 {
BIOS_ADDR => self.bios.read_32(addr), BIOS_ADDR => self.bios.read_32(addr),
EWRAM_ADDR => self.onboard_work_ram.read_32(addr & 0x3_fffc), EWRAM_ADDR => self.ewram.read_32(addr & 0x3_fffc),
IWRAM_ADDR => self.internal_work_ram.read_32(addr & 0x7ffc), IWRAM_ADDR => self.iwram.read_32(addr & 0x7ffc),
IOMEM_ADDR => { IOMEM_ADDR => {
let addr = if addr & 0xfffc == 0x8000 { let addr = if addr & 0xfffc == 0x8000 {
0x800 0x800
@ -297,8 +289,8 @@ impl Bus for SysBus {
fn read_16(&mut self, addr: Addr) -> u16 { fn read_16(&mut self, addr: Addr) -> u16 {
match addr & 0xff000000 { match addr & 0xff000000 {
BIOS_ADDR => self.bios.read_16(addr), BIOS_ADDR => self.bios.read_16(addr),
EWRAM_ADDR => self.onboard_work_ram.read_16(addr & 0x3_fffe), EWRAM_ADDR => self.ewram.read_16(addr & 0x3_fffe),
IWRAM_ADDR => self.internal_work_ram.read_16(addr & 0x7ffe), IWRAM_ADDR => self.iwram.read_16(addr & 0x7ffe),
IOMEM_ADDR => { IOMEM_ADDR => {
let addr = if addr & 0xfffe == 0x8000 { let addr = if addr & 0xfffe == 0x8000 {
0x800 0x800
@ -324,8 +316,8 @@ impl Bus for SysBus {
fn read_8(&mut self, addr: Addr) -> u8 { fn read_8(&mut self, addr: Addr) -> u8 {
match addr & 0xff000000 { match addr & 0xff000000 {
BIOS_ADDR => self.bios.read_8(addr), BIOS_ADDR => self.bios.read_8(addr),
EWRAM_ADDR => self.onboard_work_ram.read_8(addr & 0x3_ffff), EWRAM_ADDR => self.ewram.read_8(addr & 0x3_ffff),
IWRAM_ADDR => self.internal_work_ram.read_8(addr & 0x7fff), IWRAM_ADDR => self.iwram.read_8(addr & 0x7fff),
IOMEM_ADDR => { IOMEM_ADDR => {
let addr = if addr & 0xffff == 0x8000 { let addr = if addr & 0xffff == 0x8000 {
0x800 0x800
@ -351,8 +343,8 @@ impl Bus for SysBus {
fn write_32(&mut self, addr: Addr, value: u32) { fn write_32(&mut self, addr: Addr, value: u32) {
match addr & 0xff000000 { match addr & 0xff000000 {
BIOS_ADDR => {} BIOS_ADDR => {}
EWRAM_ADDR => self.onboard_work_ram.write_32(addr & 0x3_fffc, value), EWRAM_ADDR => self.ewram.write_32(addr & 0x3_fffc, value),
IWRAM_ADDR => self.internal_work_ram.write_32(addr & 0x7ffc, value), IWRAM_ADDR => self.iwram.write_32(addr & 0x7ffc, value),
IOMEM_ADDR => { IOMEM_ADDR => {
let addr = if addr & 0xfffc == 0x8000 { let addr = if addr & 0xfffc == 0x8000 {
0x800 0x800
@ -376,8 +368,8 @@ impl Bus for SysBus {
fn write_16(&mut self, addr: Addr, value: u16) { fn write_16(&mut self, addr: Addr, value: u16) {
match addr & 0xff000000 { match addr & 0xff000000 {
BIOS_ADDR => {} BIOS_ADDR => {}
EWRAM_ADDR => self.onboard_work_ram.write_16(addr & 0x3_fffe, value), EWRAM_ADDR => self.ewram.write_16(addr & 0x3_fffe, value),
IWRAM_ADDR => self.internal_work_ram.write_16(addr & 0x7ffe, value), IWRAM_ADDR => self.iwram.write_16(addr & 0x7ffe, value),
IOMEM_ADDR => { IOMEM_ADDR => {
let addr = if addr & 0xfffe == 0x8000 { let addr = if addr & 0xfffe == 0x8000 {
0x800 0x800
@ -401,8 +393,8 @@ impl Bus for SysBus {
fn write_8(&mut self, addr: Addr, value: u8) { fn write_8(&mut self, addr: Addr, value: u8) {
match addr & 0xff000000 { match addr & 0xff000000 {
BIOS_ADDR => {} BIOS_ADDR => {}
EWRAM_ADDR => self.onboard_work_ram.write_8(addr & 0x3_ffff, value), EWRAM_ADDR => self.ewram.write_8(addr & 0x3_ffff, value),
IWRAM_ADDR => self.internal_work_ram.write_8(addr & 0x7fff, value), IWRAM_ADDR => self.iwram.write_8(addr & 0x7fff, value),
IOMEM_ADDR => { IOMEM_ADDR => {
let addr = if addr & 0xffff == 0x8000 { let addr = if addr & 0xffff == 0x8000 {
0x800 0x800
@ -427,8 +419,8 @@ impl DebugRead for SysBus {
fn debug_read_8(&mut self, addr: Addr) -> u8 { fn debug_read_8(&mut self, addr: Addr) -> u8 {
match addr & 0xff000000 { match addr & 0xff000000 {
BIOS_ADDR => self.bios.debug_read_8(addr), BIOS_ADDR => self.bios.debug_read_8(addr),
EWRAM_ADDR => self.onboard_work_ram.debug_read_8(addr & 0x3_ffff), EWRAM_ADDR => self.ewram.debug_read_8(addr & 0x3_ffff),
IWRAM_ADDR => self.internal_work_ram.debug_read_8(addr & 0x7fff), IWRAM_ADDR => self.iwram.debug_read_8(addr & 0x7fff),
IOMEM_ADDR => { IOMEM_ADDR => {
let addr = if addr & 0xffff == 0x8000 { let addr = if addr & 0xffff == 0x8000 {
0x800 0x800

View file

@ -6,8 +6,6 @@ use std::path::Path;
use std::ptr; use std::ptr;
use std::time; use std::time;
use super::bus::{Addr, Bus, DebugRead};
#[cfg(not(target_arch = "wasm32"))] #[cfg(not(target_arch = "wasm32"))]
type Instant = time::Instant; type Instant = time::Instant;
#[cfg(not(target_arch = "wasm32"))] #[cfg(not(target_arch = "wasm32"))]
@ -260,33 +258,3 @@ where
Shared::new(Default::default()) Shared::new(Default::default())
} }
} }
#[derive(Serialize, Deserialize, Clone, Debug)]
#[repr(transparent)]
pub struct BoxedMemory {
pub mem: Box<[u8]>,
}
impl BoxedMemory {
pub fn new(boxed_slice: Box<[u8]>) -> BoxedMemory {
BoxedMemory { mem: boxed_slice }
}
}
impl Bus for BoxedMemory {
fn read_8(&mut self, addr: Addr) -> u8 {
unsafe { *self.mem.get_unchecked(addr as usize) }
}
fn write_8(&mut self, addr: Addr, value: u8) {
unsafe {
*self.mem.get_unchecked_mut(addr as usize) = value;
}
}
}
impl DebugRead for BoxedMemory {
fn debug_read_8(&mut self, addr: Addr) -> u8 {
self.mem[addr as usize]
}
}

View file

@ -276,7 +276,7 @@ fn main() -> Result<(), Box<dyn std::error::Error>> {
if savestate_path.is_file() { if savestate_path.is_file() {
let save = read_bin_file(&savestate_path)?; let save = read_bin_file(&savestate_path)?;
info!("Restoring state from {:?}...", savestate_path); info!("Restoring state from {:?}...", savestate_path);
gba.restore_state(&save, bios_bin.clone())?; gba.restore_state(&save)?;
info!("Restored!"); info!("Restored!");
} else { } else {
info!("Savestate not created, please create one by pressing F5"); info!("Savestate not created, please create one by pressing F5");