mGBA test suite now boots!
Fix tons of bug and reimplemented some of the core code. Add a neat feature for debug builds: When the cpu "swi 0x55" instruction, a breakpoint is triggered on the host. Former-commit-id: 959249df4374327d90b2503d7a45f8d5d27995a6
This commit is contained in:
Michel Heily
parent
c117cbe924
commit
1d088accb8
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@ -60,17 +60,7 @@ fn run_emulator(matches: &ArgMatches) -> GBAResult<()> {
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let mut core = Core::new();
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if skip_bios {
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core.gpr[13] = 0x0300_7f00;
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core.gpr_banked_r13[0] = 0x0300_7f00; // USR/SYS
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core.gpr_banked_r13[1] = 0x0300_7f00; // FIQ
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core.gpr_banked_r13[2] = 0x0300_7fa0; // IRQ
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core.gpr_banked_r13[3] = 0x0300_7fe0; // SVC
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core.gpr_banked_r13[4] = 0x0300_7f00; // ABT
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core.gpr_banked_r13[5] = 0x0300_7f00; // UND
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core.pc = 0x0800_0000;
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core.cpsr.set(0x5f);
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core.skip_bios();
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}
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let mut gba = GameBoyAdvance::new(core, bios_bin, cart, backend);
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@ -19,12 +19,15 @@ impl Core {
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ArmFormat::BX => self.exec_bx(bus, insn),
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ArmFormat::B_BL => self.exec_b_bl(bus, insn),
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ArmFormat::DP => self.exec_data_processing(bus, insn),
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ArmFormat::SWI => self.exec_swi(bus),
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ArmFormat::SWI => {
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self.software_interrupt(bus, insn.pc + 4, insn.swi_comment());
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Ok(())
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}
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ArmFormat::LDR_STR => self.exec_ldr_str(bus, insn),
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ArmFormat::LDR_STR_HS_IMM => self.exec_ldr_str_hs(bus, insn),
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ArmFormat::LDR_STR_HS_REG => self.exec_ldr_str_hs(bus, insn),
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ArmFormat::LDM_STM => self.exec_ldm_stm(bus, insn),
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ArmFormat::MRS => self.exec_mrs(bus, insn),
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ArmFormat::MRS => self.move_from_status_register(bus, insn.rd(), insn.spsr_flag()),
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ArmFormat::MSR_REG => self.exec_msr_reg(bus, insn),
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ArmFormat::MSR_FLAGS => self.exec_msr_flags(bus, insn),
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ArmFormat::MUL_MLA => self.exec_mul_mla(bus, insn),
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@ -70,40 +73,56 @@ impl Core {
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self.branch_exchange(sb, self.get_reg(insn.rn()))
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}
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fn exec_mrs(&mut self, sb: &mut SysBus, insn: ArmInstruction) -> CpuExecResult {
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let mode = self.cpsr.mode();
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let result = if insn.spsr_flag() {
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if let Some(index) = mode.spsr_index() {
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self.spsr[index].get()
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} else {
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panic!("tried to get spsr from invalid mode {}", mode)
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}
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fn move_from_status_register(
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&mut self,
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sb: &mut SysBus,
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rd: usize,
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is_spsr: bool,
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) -> CpuExecResult {
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let result = if is_spsr {
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self.spsr.get()
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} else {
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self.cpsr.get()
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};
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self.set_reg(insn.rd(), result);
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self.set_reg(rd, result);
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self.S_cycle32(sb, self.pc);
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Ok(())
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}
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fn exec_msr_reg(&mut self, sb: &mut SysBus, insn: ArmInstruction) -> CpuExecResult {
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self.exec_msr(sb, insn, self.get_reg(insn.rm()))
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self.write_status_register(sb, insn.spsr_flag(), self.get_reg(insn.rm()))
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}
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fn exec_msr(&mut self, sb: &mut SysBus, insn: ArmInstruction, value: u32) -> CpuExecResult {
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let new_psr = RegPSR::new(value);
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let old_mode = self.cpsr.mode();
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if insn.spsr_flag() {
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if let Some(index) = old_mode.spsr_index() {
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self.spsr[index] = new_psr;
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} else {
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panic!("tried to change spsr from invalid mode {}", old_mode)
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fn write_status_register(
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&mut self,
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sb: &mut SysBus,
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is_spsr: bool,
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value: u32,
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) -> CpuExecResult {
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let new_status_reg = RegPSR::new(value);
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match self.cpsr.mode() {
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CpuMode::User => {
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if is_spsr {
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panic!("User mode can't access SPSR")
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}
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self.cpsr.set_flag_bits(value);
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}
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} else {
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if old_mode != new_psr.mode() {
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self.change_mode(new_psr.mode());
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_ => {
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if is_spsr {
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self.spsr.set(value);
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} else {
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let t_bit = self.cpsr.state();
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let old_mode = self.cpsr.mode();
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self.cpsr.set(value);
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if t_bit != self.cpsr.state() {
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panic!("T bit changed from MSR");
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}
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let new_mode = new_status_reg.mode();
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if old_mode != new_mode {
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self.change_mode(old_mode, new_mode);
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}
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}
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}
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self.cpsr = new_psr;
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}
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self.S_cycle32(sb, self.pc);
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Ok(())
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@ -112,22 +131,18 @@ impl Core {
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fn exec_msr_flags(&mut self, sb: &mut SysBus, insn: ArmInstruction) -> CpuExecResult {
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self.S_cycle32(sb, self.pc);
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let op = insn.operand2()?;
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let op = self.decode_operand2(op, false)?;
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let op = self.decode_operand2(op)?;
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let old_mode = self.cpsr.mode();
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if insn.spsr_flag() {
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if let Some(index) = old_mode.spsr_index() {
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self.spsr[index].set_flag_bits(op);
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} else {
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panic!("tried to change spsr from invalid mode {}", old_mode)
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}
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self.spsr.set_flag_bits(op);
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} else {
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self.cpsr.set_flag_bits(op);
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}
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Ok(())
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}
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fn decode_operand2(&mut self, op2: BarrelShifterValue, set_flags: bool) -> CpuResult<u32> {
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fn decode_operand2(&mut self, op2: BarrelShifterValue) -> CpuResult<u32> {
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match op2 {
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BarrelShifterValue::RotatedImmediate(val, amount) => {
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let result = self.ror(val, amount, self.cpsr.C(), false, true);
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@ -135,24 +150,18 @@ impl Core {
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}
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BarrelShifterValue::ShiftedRegister(x) => {
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let result = self.register_shift(x)?;
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if set_flags {
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self.cpsr.set_C(self.bs_carry_out);
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}
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Ok(result as u32)
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Ok(result)
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}
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_ => unreachable!(),
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}
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}
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fn transfer_spsr_mode(&mut self) {
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let old_mode = self.cpsr.mode();
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if let Some(index) = old_mode.spsr_index() {
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let new_psr = self.spsr[index];
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if old_mode != new_psr.mode() {
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self.change_mode(new_psr.mode());
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}
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self.cpsr = new_psr;
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let spsr = self.spsr;
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if self.cpsr.mode() != spsr.mode() {
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self.change_mode(self.cpsr.mode(), spsr.mode());
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}
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self.cpsr = spsr;
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}
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/// Logical/Arithmetic ALU operations
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@ -160,6 +169,8 @@ impl Core {
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/// Cycles: 1S+x+y (from GBATEK)
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/// Add x=1I cycles if Op2 shifted-by-register. Add y=1S+1N cycles if Rd=R15.
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fn exec_data_processing(&mut self, sb: &mut SysBus, insn: ArmInstruction) -> CpuExecResult {
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use AluOpCode::*;
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self.S_cycle32(sb, self.pc);
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let mut op1 = if insn.rn() == REG_PC {
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(insn.pc + 8) as i32
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@ -167,7 +178,7 @@ impl Core {
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self.get_reg(insn.rn()) as i32
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};
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let s_flag = insn.set_cond_flag();
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let mut s_flag = insn.set_cond_flag();
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let opcode = insn.opcode().unwrap();
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let op2 = insn.operand2()?;
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@ -179,21 +190,28 @@ impl Core {
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}
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_ => {}
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}
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let op2 = self.decode_operand2(op2, s_flag)? as i32;
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let op2 = self.decode_operand2(op2)? as i32;
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let reg_rd = insn.rd();
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if !s_flag {
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match opcode {
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AluOpCode::TEQ | AluOpCode::CMN => {
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return self.exec_msr(sb, insn, op2 as u32);
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TEQ => {
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return self.write_status_register(sb, false, op2 as u32);
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}
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AluOpCode::TST | AluOpCode::CMP => return self.exec_mrs(sb, insn),
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CMN => {
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return self.write_status_register(sb, true, op2 as u32);
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}
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TST => return self.move_from_status_register(sb, reg_rd, false),
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CMP => return self.move_from_status_register(sb, reg_rd, true),
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_ => (),
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}
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}
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let rd = insn.rd();
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if reg_rd == REG_PC && s_flag {
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self.transfer_spsr_mode();
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s_flag = false;
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}
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use AluOpCode::*;
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let C = self.cpsr.C() as i32;
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let alu_res = if s_flag {
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let mut carry = self.bs_carry_out;
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@ -239,11 +257,10 @@ impl Core {
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};
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if let Some(result) = alu_res {
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if rd == REG_PC {
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self.transfer_spsr_mode();
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if reg_rd == REG_PC {
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self.flush_pipeline(sb);
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}
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self.set_reg(rd, result as u32);
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self.set_reg(reg_rd, result as u32);
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}
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Ok(())
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@ -30,18 +30,21 @@ pub struct Core {
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pub pc: u32,
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pub gpr: [u32; 15],
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// r13 and r14 are banked for all modes. System&User mode share them
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pub gpr_banked_r13: [u32; 6],
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pub gpr_banked_r14: [u32; 6],
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pub(super) gpr_banked_r13: [u32; 6],
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pub(super) gpr_banked_r14: [u32; 6],
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// r8-r12 are banked for fiq mode
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pub gpr_banked_old_r8_12: [u32; 5],
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pub gpr_banked_fiq_r8_12: [u32; 5],
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pub(super) gpr_banked_old_r8_12: [u32; 5],
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pub(super) gpr_banked_fiq_r8_12: [u32; 5],
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pub cpsr: RegPSR,
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pub spsr: [RegPSR; 5],
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pub(super) spsr: RegPSR,
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pub(super) spsr_bank: [RegPSR; 6],
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pub bs_carry_out: bool,
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pub(super) bs_carry_out: bool,
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pipeline_state: PipelineState,
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pipeline: [u32; 2],
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fetched_arm: u32,
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decoded_arm: u32,
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fetched_thumb: u16,
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@ -63,8 +66,10 @@ pub type CpuExecResult = CpuResult<()>;
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impl Core {
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pub fn new() -> Core {
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let mut cpsr = RegPSR::new(0x0000_00D3);
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Core {
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memreq: 0xffff_0000, // set memreq to an invalid addr so the first load cycle will be non-sequential
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cpsr: cpsr,
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..Default::default()
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}
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}
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@ -125,20 +130,20 @@ impl Core {
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}
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}
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pub fn write_32(&mut self, addr: Addr, value: u32, bus: &mut SysBus) {
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pub(super) fn write_32(&mut self, addr: Addr, value: u32, bus: &mut SysBus) {
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bus.write_32(addr & !0x3, value);
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}
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pub fn write_16(&mut self, addr: Addr, value: u16, bus: &mut SysBus) {
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pub(super) fn write_16(&mut self, addr: Addr, value: u16, bus: &mut SysBus) {
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bus.write_16(addr & !0x1, value);
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}
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pub fn write_8(&mut self, addr: Addr, value: u8, bus: &mut SysBus) {
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pub(super) fn write_8(&mut self, addr: Addr, value: u8, bus: &mut SysBus) {
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bus.write_8(addr, value);
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}
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/// Helper function for "ldr" instruction that handles misaligned addresses
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pub fn ldr_word(&mut self, addr: Addr, bus: &SysBus) -> u32 {
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pub(super) fn ldr_word(&mut self, addr: Addr, bus: &SysBus) -> u32 {
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if addr & 0x3 != 0 {
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let rotation = (addr & 0x3) << 3;
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let value = bus.read_32(addr & !0x3);
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@ -149,7 +154,7 @@ impl Core {
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}
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/// Helper function for "ldrh" instruction that handles misaligned addresses
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pub fn ldr_half(&mut self, addr: Addr, bus: &SysBus) -> u32 {
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pub(super) fn ldr_half(&mut self, addr: Addr, bus: &SysBus) -> u32 {
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if addr & 0x1 != 0 {
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let rotation = (addr & 0x1) << 3;
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let value = bus.read_16(addr & !0x1);
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@ -160,7 +165,7 @@ impl Core {
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}
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/// Helper function for "ldrsh" instruction that handles misaligned addresses
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pub fn ldr_sign_half(&mut self, addr: Addr, bus: &SysBus) -> u32 {
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pub(super) fn ldr_sign_half(&mut self, addr: Addr, bus: &SysBus) -> u32 {
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if addr & 0x1 != 0 {
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bus.read_8(addr) as i8 as i32 as u32
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} else {
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@ -172,43 +177,39 @@ impl Core {
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self.gpr.clone()
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}
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fn map_banked_registers(&mut self, curr_mode: CpuMode, new_mode: CpuMode) {
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let next_index = new_mode.bank_index();
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let curr_index = curr_mode.bank_index();
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pub(super) fn change_mode(&mut self, old_mode: CpuMode, new_mode: CpuMode) {
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let new_index = new_mode.bank_index();
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let old_index = old_mode.bank_index();
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self.gpr_banked_r13[curr_index] = self.gpr[13];
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self.gpr_banked_r14[curr_index] = self.gpr[14];
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if new_index == old_index {
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return;
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}
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self.gpr[13] = self.gpr_banked_r13[next_index];
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self.gpr[14] = self.gpr_banked_r14[next_index];
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self.spsr_bank[old_index] = self.spsr;
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self.gpr_banked_r13[old_index] = self.gpr[13];
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self.gpr_banked_r14[old_index] = self.gpr[14];
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self.spsr = self.spsr_bank[new_index];
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self.gpr[13] = self.gpr_banked_r13[new_index];
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self.gpr[14] = self.gpr_banked_r14[new_index];
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if new_mode == CpuMode::Fiq {
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for r in 0..5 {
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self.gpr_banked_old_r8_12[r] = self.gpr[r + 8];
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self.gpr[r + 8] = self.gpr_banked_fiq_r8_12[r];
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}
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} else if curr_mode == CpuMode::Fiq {
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} else if old_mode == CpuMode::Fiq {
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for r in 0..5 {
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self.gpr_banked_fiq_r8_12[r] = self.gpr[r + 8];
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self.gpr[r + 8] = self.gpr_banked_old_r8_12[r];
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}
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}
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}
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pub fn change_mode(&mut self, new_mode: CpuMode) {
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let curr_mode = self.cpsr.mode();
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// Copy CPSR to SPSR_mode
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if let Some(index) = new_mode.spsr_index() {
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self.spsr[index] = self.cpsr;
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}
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self.map_banked_registers(curr_mode, new_mode);
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// let next_index = new_mode.bank_index();
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// self.gpr_banked_r14[next_index] = self.get_next_pc();
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self.cpsr.set_mode(new_mode);
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}
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/// Resets the cpu
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pub fn reset(&mut self, sb: &mut SysBus) {
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self.exception(sb, Exception::Reset);
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self.exception(sb, Exception::Reset, 0);
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}
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pub fn word_size(&self) -> usize {
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@ -222,18 +223,18 @@ impl Core {
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self.cycles
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}
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pub fn add_cycle(&mut self) {
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pub(super) fn add_cycle(&mut self) {
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// println!("<cycle I-Cyclel> total: {}", self.cycles);
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self.cycles += 1;
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}
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pub fn add_cycles(&mut self, addr: Addr, bus: &SysBus, access: MemoryAccess) {
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pub(super) fn add_cycles(&mut self, addr: Addr, bus: &SysBus, access: MemoryAccess) {
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let cycles_to_add = 1 + bus.get_cycles(addr, access);
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// println!("<cycle {:#x} {}> took: {}", addr, access, cycles_to_add);
|
||||
self.cycles += cycles_to_add;
|
||||
}
|
||||
|
||||
pub fn cycle_type(&self, addr: Addr) -> MemoryAccessType {
|
||||
pub(super) fn cycle_type(&self, addr: Addr) -> MemoryAccessType {
|
||||
if addr == self.memreq || addr == self.memreq.wrapping_add(self.word_size() as Addr) {
|
||||
Seq
|
||||
} else {
|
||||
|
|
@ -241,7 +242,7 @@ impl Core {
|
|||
}
|
||||
}
|
||||
|
||||
pub fn get_required_multipiler_array_cycles(&self, rs: i32) -> usize {
|
||||
pub(super) fn get_required_multipiler_array_cycles(&self, rs: i32) -> usize {
|
||||
if rs & 0xff == rs {
|
||||
1
|
||||
} else if rs & 0xffff == rs {
|
||||
|
|
@ -254,42 +255,42 @@ impl Core {
|
|||
}
|
||||
|
||||
#[allow(non_snake_case)]
|
||||
pub fn S_cycle32(&mut self, sb: &SysBus, addr: u32) {
|
||||
pub(super) fn S_cycle32(&mut self, sb: &SysBus, addr: u32) {
|
||||
self.cycles += 1;
|
||||
self.cycles += sb.get_cycles(addr, Seq + MemoryAccess32);
|
||||
}
|
||||
|
||||
#[allow(non_snake_case)]
|
||||
pub fn S_cycle16(&mut self, sb: &SysBus, addr: u32) {
|
||||
pub(super) fn S_cycle16(&mut self, sb: &SysBus, addr: u32) {
|
||||
self.cycles += 1;
|
||||
self.cycles += sb.get_cycles(addr, Seq + MemoryAccess16);
|
||||
}
|
||||
|
||||
#[allow(non_snake_case)]
|
||||
pub fn S_cycle8(&mut self, sb: &SysBus, addr: u32) {
|
||||
pub(super) fn S_cycle8(&mut self, sb: &SysBus, addr: u32) {
|
||||
self.cycles += 1;
|
||||
self.cycles += sb.get_cycles(addr, Seq + MemoryAccess8);
|
||||
}
|
||||
|
||||
#[allow(non_snake_case)]
|
||||
pub fn N_cycle32(&mut self, sb: &SysBus, addr: u32) {
|
||||
pub(super) fn N_cycle32(&mut self, sb: &SysBus, addr: u32) {
|
||||
self.cycles += 1;
|
||||
self.cycles += sb.get_cycles(addr, NonSeq + MemoryAccess32);
|
||||
}
|
||||
|
||||
#[allow(non_snake_case)]
|
||||
pub fn N_cycle16(&mut self, sb: &SysBus, addr: u32) {
|
||||
pub(super) fn N_cycle16(&mut self, sb: &SysBus, addr: u32) {
|
||||
self.cycles += 1;
|
||||
self.cycles += sb.get_cycles(addr, NonSeq + MemoryAccess16);
|
||||
}
|
||||
|
||||
#[allow(non_snake_case)]
|
||||
pub fn N_cycle8(&mut self, sb: &SysBus, addr: u32) {
|
||||
pub(super) fn N_cycle8(&mut self, sb: &SysBus, addr: u32) {
|
||||
self.cycles += 1;
|
||||
self.cycles += sb.get_cycles(addr, NonSeq + MemoryAccess8);
|
||||
}
|
||||
|
||||
pub fn check_arm_cond(&self, cond: ArmCond) -> bool {
|
||||
pub(super) fn check_arm_cond(&self, cond: ArmCond) -> bool {
|
||||
use ArmCond::*;
|
||||
match cond {
|
||||
EQ => self.cpsr.Z(),
|
||||
|
|
@ -310,13 +311,8 @@ impl Core {
|
|||
}
|
||||
}
|
||||
|
||||
pub fn exec_swi(&mut self, sb: &mut SysBus) -> CpuExecResult {
|
||||
match self.cpsr.state() {
|
||||
CpuState::ARM => self.N_cycle32(sb, self.pc),
|
||||
CpuState::THUMB => self.N_cycle16(sb, self.pc),
|
||||
};
|
||||
self.exception(sb, Exception::SoftwareInterrupt);
|
||||
Ok(())
|
||||
pub(super) fn did_pipeline_flush(&self) -> bool {
|
||||
self.pipeline_state == PipelineState::Refill1
|
||||
}
|
||||
|
||||
fn step_arm_exec(&mut self, insn: u32, sb: &mut SysBus) -> CpuResult<()> {
|
||||
|
|
@ -333,48 +329,30 @@ impl Core {
|
|||
self.last_executed = None;
|
||||
}
|
||||
PipelineState::Execute => {
|
||||
let insn = ArmInstruction::decode(insn, self.pc.wrapping_sub(8))?;
|
||||
let decoded_arm = ArmInstruction::decode(insn, self.pc.wrapping_sub(8))?;
|
||||
self.gpr_previous = self.get_registers();
|
||||
self.exec_arm(sb, insn)?;
|
||||
self.exec_arm(sb, decoded_arm)?;
|
||||
if !self.did_pipeline_flush() {
|
||||
self.pc = pc.wrapping_add(4);
|
||||
}
|
||||
self.last_executed = Some(DecodedInstruction::Arm(insn));
|
||||
self.last_executed = Some(DecodedInstruction::Arm(decoded_arm));
|
||||
}
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn arm(&mut self, sb: &mut SysBus) -> CpuResult<()> {
|
||||
let pc = self.pc;
|
||||
|
||||
// fetch
|
||||
let fetched_now = sb.read_32(pc);
|
||||
let executed_now = self.decoded_arm;
|
||||
|
||||
// decode
|
||||
self.decoded_arm = self.fetched_arm;
|
||||
self.fetched_arm = fetched_now;
|
||||
|
||||
// execute
|
||||
self.step_arm_exec(executed_now, sb)?;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub fn did_pipeline_flush(&self) -> bool {
|
||||
self.pipeline_state == PipelineState::Refill1
|
||||
}
|
||||
|
||||
fn step_thumb_exec(&mut self, insn: u16, sb: &mut SysBus) -> CpuResult<()> {
|
||||
let pc = self.pc;
|
||||
match self.pipeline_state {
|
||||
PipelineState::Refill1 => {
|
||||
self.pc = pc.wrapping_add(2);
|
||||
self.pipeline_state = PipelineState::Refill2;
|
||||
self.last_executed = None;
|
||||
}
|
||||
PipelineState::Refill2 => {
|
||||
self.pc = pc.wrapping_add(2);
|
||||
self.pipeline_state = PipelineState::Execute;
|
||||
self.last_executed = None;
|
||||
}
|
||||
PipelineState::Execute => {
|
||||
let insn = ThumbInstruction::decode(insn, self.pc.wrapping_sub(4))?;
|
||||
|
|
@ -389,23 +367,7 @@ impl Core {
|
|||
Ok(())
|
||||
}
|
||||
|
||||
fn thumb(&mut self, sb: &mut SysBus) -> CpuResult<()> {
|
||||
let pc = self.pc;
|
||||
|
||||
// fetch
|
||||
let fetched_now = sb.read_16(pc);
|
||||
let executed_now = self.decoded_thumb;
|
||||
|
||||
// decode
|
||||
self.decoded_thumb = self.fetched_thumb;
|
||||
self.fetched_thumb = fetched_now;
|
||||
|
||||
// execute
|
||||
self.step_thumb_exec(executed_now, sb)?;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub fn flush_pipeline(&mut self, sb: &mut SysBus) {
|
||||
pub(super) fn flush_pipeline(&mut self, sb: &mut SysBus) {
|
||||
self.pipeline_state = PipelineState::Refill1;
|
||||
match self.cpsr.state() {
|
||||
CpuState::ARM => {
|
||||
|
|
@ -422,9 +384,20 @@ impl Core {
|
|||
/// Perform a pipeline step
|
||||
/// If an instruction was executed in this step, return it.
|
||||
pub fn step(&mut self, bus: &mut SysBus) -> CpuResult<()> {
|
||||
let pc = self.pc;
|
||||
|
||||
let fetched_now = match self.cpsr.state() {
|
||||
CpuState::ARM => bus.read_32(pc),
|
||||
CpuState::THUMB => bus.read_16(pc) as u32,
|
||||
};
|
||||
|
||||
let insn = self.pipeline[0];
|
||||
self.pipeline[0] = self.pipeline[1];
|
||||
self.pipeline[1] = fetched_now;
|
||||
|
||||
match self.cpsr.state() {
|
||||
CpuState::ARM => self.arm(bus),
|
||||
CpuState::THUMB => self.thumb(bus),
|
||||
CpuState::ARM => self.step_arm_exec(insn, bus),
|
||||
CpuState::THUMB => self.step_thumb_exec(insn as u16, bus),
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -454,6 +427,25 @@ impl Core {
|
|||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub fn get_cpu_state(&self) -> CpuState {
|
||||
self.cpsr.state()
|
||||
}
|
||||
|
||||
pub fn skip_bios(&mut self) {
|
||||
self.gpr_banked_r13[0] = 0x0300_7f00; // USR/SYS
|
||||
self.gpr_banked_r13[1] = 0x0300_7f00; // FIQ
|
||||
self.gpr_banked_r13[2] = 0x0300_7fa0; // IRQ
|
||||
self.gpr_banked_r13[3] = 0x0300_7fe0; // SVC
|
||||
self.gpr_banked_r13[4] = 0x0300_7f00; // ABT
|
||||
self.gpr_banked_r13[5] = 0x0300_7f00; // UND
|
||||
|
||||
self.gpr[13] = 0x0300_7f00;
|
||||
self.gpr[14] = 0x0800_0000;
|
||||
self.pc = 0x0800_0000;
|
||||
|
||||
self.cpsr.set(0x5f);
|
||||
}
|
||||
}
|
||||
|
||||
impl fmt::Display for Core {
|
||||
|
|
|
|||
|
|
@ -18,24 +18,19 @@ pub enum Exception {
|
|||
Fiq = 0x1c,
|
||||
}
|
||||
|
||||
impl From<Exception> for CpuMode {
|
||||
/// Return cpu mode upon entry
|
||||
fn from(e: Exception) -> CpuMode {
|
||||
use Exception::*;
|
||||
match e {
|
||||
Reset | SoftwareInterrupt | Reserved => CpuMode::Supervisor,
|
||||
PrefatchAbort | DataAbort => CpuMode::Abort,
|
||||
UndefinedInstruction => CpuMode::Undefined,
|
||||
Irq => CpuMode::Irq,
|
||||
Fiq => CpuMode::Fiq,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl Core {
|
||||
pub fn exception(&mut self, sb: &mut SysBus, e: Exception) {
|
||||
let vector = e as u32;
|
||||
let new_mode = CpuMode::from(e);
|
||||
pub fn exception(&mut self, sb: &mut SysBus, e: Exception, lr: u32) {
|
||||
use Exception::*;
|
||||
let (new_mode, irq_disable, fiq_disable) = match e {
|
||||
Reset => (CpuMode::Supervisor, true, true),
|
||||
UndefinedInstruction => (CpuMode::Undefined, false, false),
|
||||
SoftwareInterrupt => (CpuMode::Supervisor, true, false),
|
||||
DataAbort => (CpuMode::Abort, false, false),
|
||||
PrefatchAbort => (CpuMode::Abort, false, false),
|
||||
Reserved => panic!("Cpu reserved exception"),
|
||||
Irq => (CpuMode::Irq, true, false),
|
||||
Fiq => (CpuMode::Fiq, true, true),
|
||||
};
|
||||
if self.verbose {
|
||||
println!(
|
||||
"{}: {:?}, pc: {:#x}, new_mode: {:?} old_mode: {:?}",
|
||||
|
|
@ -47,19 +42,46 @@ impl Core {
|
|||
);
|
||||
}
|
||||
|
||||
self.change_mode(new_mode);
|
||||
self.gpr[REG_LR] = self.get_next_pc() + (self.word_size() as u32);
|
||||
let new_bank = new_mode.bank_index();
|
||||
self.spsr_bank[new_bank] = self.cpsr;
|
||||
self.gpr_banked_r14[new_bank] = lr;
|
||||
self.change_mode(self.cpsr.mode(), new_mode);
|
||||
|
||||
// Set appropriate CPSR bits
|
||||
self.cpsr.set_state(CpuState::ARM);
|
||||
self.cpsr.set_mode(new_mode);
|
||||
self.cpsr.set_irq_disabled(true);
|
||||
if e == Exception::Reset || e == Exception::Fiq {
|
||||
if irq_disable {
|
||||
self.cpsr.set_irq_disabled(true);
|
||||
}
|
||||
if fiq_disable {
|
||||
self.cpsr.set_fiq_disabled(true);
|
||||
}
|
||||
|
||||
// Set PC to vector address
|
||||
self.pc = vector;
|
||||
self.pc = e as u32;
|
||||
self.flush_pipeline(sb);
|
||||
}
|
||||
|
||||
pub fn irq(&mut self, sb: &mut SysBus) {
|
||||
if !self.cpsr.irq_disabled() {
|
||||
let lr = self.get_next_pc() + 4;
|
||||
self.exception(sb, Exception::Irq, lr)
|
||||
}
|
||||
}
|
||||
|
||||
pub fn software_interrupt(&mut self, sb: &mut SysBus, lr: u32, cmt: u32) {
|
||||
match self.cpsr.state() {
|
||||
CpuState::ARM => self.N_cycle32(sb, self.pc),
|
||||
CpuState::THUMB => self.N_cycle16(sb, self.pc),
|
||||
};
|
||||
if cmt == 0x55 {
|
||||
#[cfg(debug_assertions)]
|
||||
{
|
||||
println!("Special breakpoint detected!");
|
||||
host_breakpoint!();
|
||||
}
|
||||
} else {
|
||||
self.exception(sb, Exception::SoftwareInterrupt, lr);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@ impl From<bool> for CpuState {
|
|||
}
|
||||
}
|
||||
|
||||
#[derive(Debug, Clone, Copy)]
|
||||
#[derive(Debug, Clone, Copy, Default)]
|
||||
pub struct RegPSR {
|
||||
raw: u32,
|
||||
}
|
||||
|
|
@ -37,13 +37,6 @@ fn clear_reserved(n: u32) -> u32 {
|
|||
n & !RESERVED_BIT_MASK
|
||||
}
|
||||
|
||||
impl Default for RegPSR {
|
||||
fn default() -> RegPSR {
|
||||
let mut psr = RegPSR::new(0);
|
||||
psr.set_mode(CpuMode::Supervisor);
|
||||
psr
|
||||
}
|
||||
}
|
||||
impl RegPSR {
|
||||
pub const FLAG_BITMASK: u32 = 0xf000_0000;
|
||||
|
||||
|
|
|
|||
|
|
@ -562,7 +562,10 @@ impl Core {
|
|||
ThumbFormat::PushPop => self.exec_thumb_push_pop(bus, insn),
|
||||
ThumbFormat::LdmStm => self.exec_thumb_ldm_stm(bus, insn),
|
||||
ThumbFormat::BranchConditional => self.exec_thumb_branch_with_cond(bus, insn),
|
||||
ThumbFormat::Swi => self.exec_swi(bus),
|
||||
ThumbFormat::Swi => {
|
||||
self.software_interrupt(bus, insn.pc + 2, (insn.raw & 0xff) as u32);
|
||||
Ok(())
|
||||
}
|
||||
ThumbFormat::Branch => self.exec_thumb_branch(bus, insn),
|
||||
ThumbFormat::BranchLongWithLink => self.exec_thumb_branch_long_with_link(bus, insn),
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/// Struct containing everything
|
||||
use super::arm7tdmi::{exception::Exception, Core, DecodedInstruction};
|
||||
use super::arm7tdmi::{exception::Exception, Core, CpuState, DecodedInstruction};
|
||||
use super::cartridge::Cartridge;
|
||||
use super::gpu::*;
|
||||
use super::interrupt::*;
|
||||
|
|
@ -64,6 +64,9 @@ impl GameBoyAdvance {
|
|||
};
|
||||
|
||||
if !io.dmac.perform_work(&mut self.sysbus, &mut irqs) {
|
||||
if io.intc.irq_pending() {
|
||||
self.cpu.irq(&mut self.sysbus);
|
||||
}
|
||||
self.cpu.step(&mut self.sysbus).unwrap();
|
||||
}
|
||||
|
||||
|
|
@ -81,11 +84,6 @@ impl GameBoyAdvance {
|
|||
}
|
||||
}
|
||||
|
||||
if !self.cpu.cpsr.irq_disabled() {
|
||||
io.intc.request_irqs(irqs);
|
||||
if io.intc.irq_pending() {
|
||||
self.cpu.exception(&mut self.sysbus, Exception::Irq);
|
||||
}
|
||||
}
|
||||
io.intc.request_irqs(irqs);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -33,14 +33,11 @@ impl InterruptController {
|
|||
}
|
||||
|
||||
pub fn request_irqs(&mut self, flags: IrqBitmask) {
|
||||
if !self.interrupt_master_enable {
|
||||
return;
|
||||
}
|
||||
self.interrupt_flags.0 |= flags.0 & self.interrupt_enable.0;
|
||||
self.interrupt_flags.0 |= flags.0;
|
||||
}
|
||||
|
||||
pub fn irq_pending(&self) -> bool {
|
||||
self.interrupt_master_enable & (self.interrupt_flags.0 != 0)
|
||||
self.interrupt_master_enable & ((self.interrupt_flags.0 & self.interrupt_enable.0) != 0)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -377,7 +377,7 @@ impl Debugger {
|
|||
"d" | "disass" => {
|
||||
let (addr, n) = self.get_disassembler_args(args)?;
|
||||
|
||||
let m = match self.gba.cpu.cpsr.state() {
|
||||
let m = match self.gba.cpu.get_cpu_state() {
|
||||
CpuState::ARM => DisassMode::ModeArm,
|
||||
CpuState::THUMB => DisassMode::ModeThumb,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,3 +1,6 @@
|
|||
#![feature(asm)]
|
||||
#![feature(core_intrinsics)]
|
||||
|
||||
#[macro_use]
|
||||
extern crate enum_primitive_derive;
|
||||
extern crate num;
|
||||
|
|
|
|||
|
|
@ -18,3 +18,12 @@ macro_rules! index2d {
|
|||
(($w as $t) * ($y as $t) + ($x as $t)) as $t
|
||||
};
|
||||
}
|
||||
|
||||
macro_rules! host_breakpoint {
|
||||
() => {
|
||||
#[cfg(debug_assertions)]
|
||||
unsafe {
|
||||
::std::intrinsics::breakpoint()
|
||||
}
|
||||
};
|
||||
}
|
||||
|
|
|
|||
Reference in a new issue