diff --git a/src/core/sysbus.rs b/src/core/sysbus.rs
index 9bb1879..8a5ee91 100644
--- a/src/core/sysbus.rs
+++ b/src/core/sysbus.rs
@@ -79,35 +79,29 @@ impl BoxedMemory {
 
 impl Bus for BoxedMemory {
     fn read_32(&self, addr: Addr) -> u32 {
-        (&self.mem[addr as usize..])
-            .read_u32::<LittleEndian>()
-            .unwrap()
+        self.read_16(addr) as u32 | (self.read_16(addr + 2) as u32) << 16
     }
 
     fn read_16(&self, addr: Addr) -> u16 {
-        (&self.mem[addr as usize..])
-            .read_u16::<LittleEndian>()
-            .unwrap()
+        self.read_8(addr) as u16 | (self.read_8(addr+1) as u16) << 8
     }
 
     fn read_8(&self, addr: Addr) -> u8 {
-        (&self.mem[addr as usize..])[0]
+        self.mem[addr as usize]
     }
 
     fn write_32(&mut self, addr: Addr, value: u32) {
-        (&mut self.mem[addr as usize..])
-            .write_u32::<LittleEndian>(value)
-            .unwrap()
+        self.write_16(addr, (value & 0xffff) as u16);
+        self.write_16(addr + 2, (value >> 16) as u16);
     }
 
     fn write_16(&mut self, addr: Addr, value: u16) {
-        (&mut self.mem[addr as usize..])
-            .write_u16::<LittleEndian>(value)
-            .unwrap()
+        self.write_8(addr, (value & 0xff) as u8);
+        self.write_8(addr + 1, ((value >> 8) & 0xff) as u8);
     }
 
     fn write_8(&mut self, addr: Addr, value: u8) {
-        (&mut self.mem[addr as usize..]).write_u8(value).unwrap()
+        self.mem[addr as usize] = value;
     }
 }