optimize: CPU Pipeline optimization part 1
In preperation for later optimization in the CPU pipeline implementation, this commit refactors the arm/thumb exec functions to return a CpuAction (Whether to advance the program counter or to flush the pipeline) Currently, a lot of host cycles are wasted in the arm7tdmi pipeline Refill1 & Refill2 states. Optimizing these steps out would make the CPU a bit faster. Former-commit-id: 9be7966eaad22cceeb443fcc5823bbd945284027
This commit is contained in:
Michel Heily
parent
7736154b50
commit
1f79205f51
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@ -2,6 +2,7 @@ use crate::bit::BitIndex;
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use super::super::alu::*;
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use crate::core::arm7tdmi::psr::RegPSR;
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use crate::core::arm7tdmi::CpuAction;
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use crate::core::arm7tdmi::{Core, Addr, CpuMode, CpuState, REG_LR, REG_PC};
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use crate::core::sysbus::SysBus;
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use crate::core::Bus;
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@ -9,10 +10,10 @@ use crate::core::Bus;
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use super::*;
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impl Core {
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pub fn exec_arm(&mut self, bus: &mut SysBus, insn: ArmInstruction) {
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pub fn exec_arm(&mut self, bus: &mut SysBus, insn: ArmInstruction) -> CpuAction {
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if !self.check_arm_cond(insn.cond) {
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self.S_cycle32(bus, self.pc);
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return;
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return CpuAction::AdvancePC;
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}
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match insn.fmt {
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ArmFormat::BX => self.exec_bx(bus, insn),
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@ -20,6 +21,7 @@ impl Core {
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ArmFormat::DP => self.exec_data_processing(bus, insn),
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ArmFormat::SWI => {
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self.software_interrupt(bus, self.pc - 4, insn.swi_comment());
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CpuAction::FlushPipeline
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}
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ArmFormat::LDR_STR => self.exec_ldr_str(bus, insn),
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ArmFormat::LDR_STR_HS_IMM => self.exec_ldr_str_hs(bus, insn),
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@ -35,18 +37,18 @@ impl Core {
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}
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/// Cycles 2S+1N
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fn exec_b_bl(&mut self, sb: &mut SysBus, insn: ArmInstruction) {
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fn exec_b_bl(&mut self, sb: &mut SysBus, insn: ArmInstruction) -> CpuAction {
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self.S_cycle32(sb, self.pc);
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if insn.link_flag() {
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self.set_reg(REG_LR, (insn.pc + (self.word_size() as u32)) & !0b1);
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}
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self.pc = (self.pc as i32).wrapping_add(insn.branch_offset()) as u32 & !1;
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self.flush_pipeline32(sb);
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CpuAction::FlushPipeline
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}
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pub fn branch_exchange(&mut self, sb: &mut SysBus, mut addr: Addr) {
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pub fn branch_exchange(&mut self, sb: &mut SysBus, mut addr: Addr) -> CpuAction {
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match self.cpsr.state() {
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CpuState::ARM => self.S_cycle32(sb, self.pc),
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CpuState::THUMB => self.S_cycle16(sb, self.pc),
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@ -54,18 +56,18 @@ impl Core {
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if addr.bit(0) {
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addr = addr & !0x1;
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self.cpsr.set_state(CpuState::THUMB);
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self.pc = addr;
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self.flush_pipeline16(sb);
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} else {
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addr = addr & !0x3;
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self.cpsr.set_state(CpuState::ARM);
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self.pc = addr;
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self.flush_pipeline32(sb);
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}
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self.pc = addr;
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CpuAction::FlushPipeline
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}
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/// Cycles 2S+1N
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fn exec_bx(&mut self, sb: &mut SysBus, insn: ArmInstruction) {
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fn exec_bx(&mut self, sb: &mut SysBus, insn: ArmInstruction) -> CpuAction {
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self.branch_exchange(sb, self.get_reg(insn.rn()))
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}
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@ -74,7 +76,7 @@ impl Core {
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sb: &mut SysBus,
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rd: usize,
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is_spsr: bool,
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) {
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) -> CpuAction {
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let result = if is_spsr {
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self.spsr.get()
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} else {
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@ -82,9 +84,11 @@ impl Core {
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};
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self.set_reg(rd, result);
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self.S_cycle32(sb, self.pc);
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CpuAction::AdvancePC
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}
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fn exec_msr_reg(&mut self, sb: &mut SysBus, insn: ArmInstruction) {
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fn exec_msr_reg(&mut self, sb: &mut SysBus, insn: ArmInstruction) -> CpuAction {
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self.write_status_register(sb, insn.spsr_flag(), self.get_reg(insn.rm()))
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}
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@ -93,7 +97,7 @@ impl Core {
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sb: &mut SysBus,
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is_spsr: bool,
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value: u32,
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) {
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) -> CpuAction {
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let new_status_reg = RegPSR::new(value);
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match self.cpsr.mode() {
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CpuMode::User => {
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@ -120,9 +124,11 @@ impl Core {
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}
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}
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self.S_cycle32(sb, self.pc);
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CpuAction::AdvancePC
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}
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fn exec_msr_flags(&mut self, sb: &mut SysBus, insn: ArmInstruction) {
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fn exec_msr_flags(&mut self, sb: &mut SysBus, insn: ArmInstruction) -> CpuAction {
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self.S_cycle32(sb, self.pc);
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let op = insn.operand2();
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let op = self.decode_operand2(op);
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@ -132,6 +138,7 @@ impl Core {
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} else {
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self.cpsr.set_flag_bits(op);
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}
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CpuAction::AdvancePC
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}
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fn decode_operand2(&mut self, op2: BarrelShifterValue) -> u32 {
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@ -158,7 +165,7 @@ impl Core {
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///
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/// Cycles: 1S+x+y (from GBATEK)
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/// Add x=1I cycles if Op2 shifted-by-register. Add y=1S+1N cycles if Rd=R15.
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fn exec_data_processing(&mut self, sb: &mut SysBus, insn: ArmInstruction) {
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fn exec_data_processing(&mut self, sb: &mut SysBus, insn: ArmInstruction) -> CpuAction {
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use AluOpCode::*;
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self.S_cycle32(sb, self.pc);
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@ -246,13 +253,15 @@ impl Core {
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})
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};
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if let Some(result) = alu_res {
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let mut result = CpuAction::AdvancePC;
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if let Some(alu_res) = alu_res {
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self.set_reg(reg_rd, alu_res as u32);
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if reg_rd == REG_PC {
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self.flush_pipeline32(sb);
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result = CpuAction::FlushPipeline;
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}
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self.set_reg(reg_rd, result as u32);
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}
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result
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}
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/// Memory Load/Store
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@ -262,7 +271,9 @@ impl Core {
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/// STR{cond}{B}{T} Rd,<Address> | 2N | ---- | [Rn+/-<offset>]=Rd
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/// ------------------------------------------------------------------------------
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/// For LDR, add y=1S+1N if Rd=R15.
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fn exec_ldr_str(&mut self, sb: &mut SysBus, insn: ArmInstruction) {
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fn exec_ldr_str(&mut self, sb: &mut SysBus, insn: ArmInstruction) -> CpuAction {
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let mut result = CpuAction::AdvancePC;
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let load = insn.load_flag();
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let pre_index = insn.pre_index_flag();
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let writeback = insn.write_back_flag();
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@ -303,7 +314,7 @@ impl Core {
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self.add_cycle();
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if dest_reg == REG_PC {
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self.flush_pipeline32(sb);
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result = CpuAction::FlushPipeline;
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}
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} else {
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let value = if dest_reg == REG_PC {
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@ -333,9 +344,12 @@ impl Core {
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self.change_mode(self.cpsr.mode(), old_mode);
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}
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result
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}
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fn exec_ldr_str_hs(&mut self, sb: &mut SysBus, insn: ArmInstruction) {
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fn exec_ldr_str_hs(&mut self, sb: &mut SysBus, insn: ArmInstruction) -> CpuAction {
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let mut result = CpuAction::AdvancePC;
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let load = insn.load_flag();
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let pre_index = insn.pre_index_flag();
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let writeback = insn.write_back_flag();
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@ -384,7 +398,7 @@ impl Core {
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self.add_cycle();
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if dest_reg == REG_PC {
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self.flush_pipeline32(sb);
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result = CpuAction::FlushPipeline;
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}
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} else {
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let value = if dest_reg == REG_PC {
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@ -411,9 +425,12 @@ impl Core {
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}
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}
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result
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}
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fn exec_ldm_stm(&mut self, sb: &mut SysBus, insn: ArmInstruction) {
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fn exec_ldm_stm(&mut self, sb: &mut SysBus, insn: ArmInstruction) -> CpuAction {
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let mut result = CpuAction::AdvancePC;
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let mut full = insn.pre_index_flag();
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let ascending = insn.add_offset_flag();
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let s_flag = insn.raw.bit(22);
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@ -487,7 +504,7 @@ impl Core {
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if psr_transfer {
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self.transfer_spsr_mode();
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}
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self.flush_pipeline32(sb);
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result = CpuAction::FlushPipeline;
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}
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if !full {
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@ -541,7 +558,7 @@ impl Core {
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if is_load {
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let val = self.ldr_word(addr, sb);
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self.set_reg(REG_PC, val & !3);
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self.flush_pipeline32(sb);
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result = CpuAction::FlushPipeline;
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} else {
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self.write_32(addr, self.pc + 4, sb);
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}
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@ -556,9 +573,10 @@ impl Core {
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self.set_reg(base_reg, addr as u32);
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}
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result
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}
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fn exec_mul_mla(&mut self, sb: &mut SysBus, insn: ArmInstruction) {
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fn exec_mul_mla(&mut self, sb: &mut SysBus, insn: ArmInstruction) -> CpuAction {
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let (rd, rn, rs, rm) = (insn.rd(), insn.rn(), insn.rs(), insn.rm());
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// check validity
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@ -589,9 +607,11 @@ impl Core {
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}
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self.S_cycle32(sb, self.pc);
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CpuAction::AdvancePC
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}
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fn exec_mull_mlal(&mut self, sb: &mut SysBus, insn: ArmInstruction) {
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fn exec_mull_mlal(&mut self, sb: &mut SysBus, insn: ArmInstruction) -> CpuAction {
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let (rd_hi, rd_lo, rn, rs, rm) =
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(insn.rd_hi(), insn.rd_lo(), insn.rn(), insn.rs(), insn.rm());
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@ -632,11 +652,12 @@ impl Core {
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}
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self.S_cycle32(sb, self.pc);
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CpuAction::AdvancePC
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}
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fn exec_arm_swp(&mut self, sb: &mut SysBus, insn: ArmInstruction) {
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fn exec_arm_swp(&mut self, sb: &mut SysBus, insn: ArmInstruction) -> CpuAction {
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let base_addr = self.get_reg(insn.rn());
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self.add_cycle();
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if insn.transfer_size() == 1 {
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let t = sb.read_8(base_addr);
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self.N_cycle8(sb, base_addr);
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@ -650,6 +671,9 @@ impl Core {
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self.S_cycle32(sb, base_addr);
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self.set_reg(insn.rd(), t as u32);
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}
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self.add_cycle();
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self.N_cycle32(sb, self.pc);
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CpuAction::AdvancePC
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}
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}
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@ -6,6 +6,7 @@ use ansi_term::{Colour, Style};
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use super::reg_string;
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use serde::{Deserialize, Serialize};
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use super::CpuAction;
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pub use super::exception::Exception;
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use super::{
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arm::*, psr::RegPSR, thumb::ThumbInstruction, Addr, CpuMode, CpuResult, CpuState,
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@ -312,6 +313,23 @@ impl Core {
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self.pipeline_state != PipelineState::Execute
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}
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fn handle_exec_result(&mut self, sb: &mut SysBus, exec_result: CpuAction) {
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match self.cpsr.state() {
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CpuState::ARM => {
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match exec_result {
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CpuAction::AdvancePC => self.advance_arm(),
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CpuAction::FlushPipeline => self.flush_pipeline32(sb),
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}
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}
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CpuState::THUMB => {
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match exec_result {
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CpuAction::AdvancePC => self.advance_thumb(),
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CpuAction::FlushPipeline => self.flush_pipeline16(sb),
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}
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}
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}
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}
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fn step_arm_exec(&mut self, insn: u32, sb: &mut SysBus) {
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let pc = self.pc;
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match self.pipeline_state {
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@ -331,11 +349,9 @@ impl Core {
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{
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self.gpr_previous = self.get_registers();
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}
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self.exec_arm(sb, decoded_arm);
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if !self.did_pipeline_flush() {
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self.pc = pc.wrapping_add(4);
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}
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self.last_executed = Some(DecodedInstruction::Arm(decoded_arm));
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let result = self.exec_arm(sb, decoded_arm);
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self.handle_exec_result(sb, result);
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}
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}
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}
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@ -359,27 +375,37 @@ impl Core {
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{
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self.gpr_previous = self.get_registers();
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}
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self.exec_thumb(sb, decoded_thumb);
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if !self.did_pipeline_flush() {
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self.pc = pc.wrapping_add(2);
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}
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self.last_executed = Some(DecodedInstruction::Thumb(decoded_thumb));
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let result = self.exec_thumb(sb, decoded_thumb);
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self.handle_exec_result(sb, result);
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}
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}
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}
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#[inline]
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pub(super) fn flush_pipeline16(&mut self, sb: &mut SysBus) {
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self.pipeline_state = PipelineState::Refill1;
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self.N_cycle16(sb, self.pc);
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self.S_cycle16(sb, self.pc + 2);
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}
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#[inline]
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pub(super) fn flush_pipeline32(&mut self, sb: &mut SysBus) {
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self.pipeline_state = PipelineState::Refill1;
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self.N_cycle32(sb, self.pc);
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self.S_cycle32(sb, self.pc + 4);
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}
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#[inline]
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pub(super) fn advance_thumb(&mut self) {
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self.pc = self.pc.wrapping_add(2)
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}
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#[inline]
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pub(super) fn advance_arm(&mut self) {
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self.pc = self.pc.wrapping_add(4)
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}
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// fn trace_opcode(&self, insn: u32) {
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// if self.trace_opcodes && self.pipeline_state == PipelineState::Execute {
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// println!("[{:08X}] PC=0x{:08x} | ", insn, self.pc);
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@ -56,7 +56,6 @@ impl Core {
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// Set PC to vector address
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self.pc = e as u32;
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self.flush_pipeline32(sb);
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}
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pub fn irq(&mut self, sb: &mut SysBus) {
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@ -65,7 +64,8 @@ impl Core {
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}
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if !self.cpsr.irq_disabled() {
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let lr = self.get_next_pc() + 4;
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self.exception(sb, Exception::Irq, lr)
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self.exception(sb, Exception::Irq, lr);
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self.flush_pipeline32(sb);
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}
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}
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@ -23,6 +23,11 @@ pub const REG_SP: usize = 13;
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pub(self) use crate::core::Addr;
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pub enum CpuAction {
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AdvancePC,
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FlushPipeline
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}
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#[derive(Serialize, Deserialize, Debug, PartialEq, Copy, Clone)]
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pub enum DecodedInstruction {
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Arm(ArmInstruction),
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@ -22,7 +22,7 @@ impl Core {
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&mut self,
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sb: &mut SysBus,
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insn: ThumbInstruction,
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) {
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) -> CpuAction {
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let rd = (insn.raw & 0b111) as usize;
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let rs = insn.raw.bit_range(3..6) as usize;
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@ -33,10 +33,12 @@ impl Core {
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self.alu_update_flags(op2, false, self.bs_carry_out, self.cpsr.V());
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self.S_cycle16(sb, self.pc + 2);
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CpuAction::AdvancePC
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}
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/// Format 2
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fn exec_thumb_add_sub(&mut self, sb: &mut SysBus, insn: ThumbInstruction) {
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fn exec_thumb_add_sub(&mut self, sb: &mut SysBus, insn: ThumbInstruction) -> CpuAction {
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let rd = (insn.raw & 0b111) as usize;
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let op1 = self.get_reg(insn.rs());
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let op2 = if insn.is_immediate_operand() {
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@ -56,6 +58,8 @@ impl Core {
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self.set_reg(rd, result as u32);
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self.S_cycle16(sb, self.pc + 2);
|
||||
|
||||
CpuAction::AdvancePC
|
||||
}
|
||||
|
||||
/// Format 3
|
||||
|
|
@ -63,7 +67,7 @@ impl Core {
|
|||
&mut self,
|
||||
sb: &mut SysBus,
|
||||
insn: ThumbInstruction,
|
||||
) {
|
||||
) -> CpuAction {
|
||||
use OpFormat3::*;
|
||||
let op = insn.format3_op();
|
||||
let rd = insn.raw.bit_range(8..11) as usize;
|
||||
|
|
@ -82,10 +86,12 @@ impl Core {
|
|||
self.gpr[rd] = result as u32;
|
||||
}
|
||||
self.S_cycle16(sb, self.pc + 2);
|
||||
|
||||
CpuAction::AdvancePC
|
||||
}
|
||||
|
||||
/// Format 4
|
||||
fn exec_thumb_alu_ops(&mut self, sb: &mut SysBus, insn: ThumbInstruction) {
|
||||
fn exec_thumb_alu_ops(&mut self, sb: &mut SysBus, insn: ThumbInstruction) -> CpuAction {
|
||||
let rd = (insn.raw & 0b111) as usize;
|
||||
let rs = insn.rs();
|
||||
let dst = self.get_reg(rd);
|
||||
|
|
@ -137,6 +143,8 @@ impl Core {
|
|||
self.set_reg(rd, result as u32);
|
||||
}
|
||||
self.S_cycle16(sb, self.pc + 2);
|
||||
|
||||
CpuAction::AdvancePC
|
||||
}
|
||||
|
||||
/// Format 5
|
||||
|
|
@ -144,7 +152,7 @@ impl Core {
|
|||
&mut self,
|
||||
sb: &mut SysBus,
|
||||
insn: ThumbInstruction,
|
||||
) {
|
||||
) -> CpuAction {
|
||||
let op = insn.format5_op();
|
||||
let rd = (insn.raw & 0b111) as usize;
|
||||
let dst_reg = if insn.flag(ThumbInstruction::FLAG_H1) {
|
||||
|
|
@ -160,15 +168,15 @@ impl Core {
|
|||
let op1 = self.get_reg(dst_reg);
|
||||
let op2 = self.get_reg(src_reg);
|
||||
|
||||
let mut result = CpuAction::AdvancePC;
|
||||
match op {
|
||||
OpFormat5::BX => {
|
||||
self.branch_exchange(sb, self.get_reg(src_reg));
|
||||
return;
|
||||
return self.branch_exchange(sb, self.get_reg(src_reg));
|
||||
},
|
||||
OpFormat5::ADD => {
|
||||
self.set_reg(dst_reg, op1.wrapping_add(op2));
|
||||
if dst_reg == REG_PC {
|
||||
self.flush_pipeline16(sb);
|
||||
result = CpuAction::FlushPipeline
|
||||
}
|
||||
}
|
||||
OpFormat5::CMP => {
|
||||
|
|
@ -180,15 +188,17 @@ impl Core {
|
|||
OpFormat5::MOV => {
|
||||
self.set_reg(dst_reg, op2 as u32);
|
||||
if dst_reg == REG_PC {
|
||||
self.flush_pipeline16(sb);
|
||||
result = CpuAction::FlushPipeline;
|
||||
}
|
||||
}
|
||||
}
|
||||
self.S_cycle16(sb, self.pc + 2);
|
||||
|
||||
result
|
||||
}
|
||||
|
||||
/// Format 6
|
||||
fn exec_thumb_ldr_pc(&mut self, sb: &mut SysBus, insn: ThumbInstruction) {
|
||||
fn exec_thumb_ldr_pc(&mut self, sb: &mut SysBus, insn: ThumbInstruction) -> CpuAction {
|
||||
let rd = insn.raw.bit_range(8..11) as usize;
|
||||
|
||||
let ofs = insn.word8() as Addr;
|
||||
|
|
@ -203,6 +213,7 @@ impl Core {
|
|||
// +1I
|
||||
self.add_cycle();
|
||||
|
||||
CpuAction::AdvancePC
|
||||
}
|
||||
|
||||
fn do_exec_thumb_ldr_str(
|
||||
|
|
@ -211,7 +222,7 @@ impl Core {
|
|||
insn: ThumbInstruction,
|
||||
addr: Addr,
|
||||
is_transferring_bytes: bool,
|
||||
) {
|
||||
) -> CpuAction {
|
||||
let rd = (insn.raw & 0b111) as usize;
|
||||
if insn.is_load() {
|
||||
let data = if is_transferring_bytes {
|
||||
|
|
@ -238,6 +249,8 @@ impl Core {
|
|||
}
|
||||
|
||||
self.N_cycle16(sb, self.pc + 2);
|
||||
|
||||
CpuAction::AdvancePC
|
||||
}
|
||||
|
||||
/// Format 7
|
||||
|
|
@ -245,14 +258,14 @@ impl Core {
|
|||
&mut self,
|
||||
bus: &mut SysBus,
|
||||
insn: ThumbInstruction,
|
||||
) {
|
||||
) -> CpuAction {
|
||||
let rb = insn.raw.bit_range(3..6) as usize;
|
||||
let addr = self.gpr[rb].wrapping_add(self.gpr[insn.ro()]);
|
||||
self.do_exec_thumb_ldr_str(bus, insn, addr, insn.raw.bit(10))
|
||||
}
|
||||
|
||||
/// Format 8
|
||||
fn exec_thumb_ldr_str_shb(&mut self, sb: &mut SysBus, insn: ThumbInstruction) {
|
||||
fn exec_thumb_ldr_str_shb(&mut self, sb: &mut SysBus, insn: ThumbInstruction) -> CpuAction {
|
||||
let rb = insn.raw.bit_range(3..6) as usize;
|
||||
let rd = (insn.raw & 0b111) as usize;
|
||||
|
||||
|
|
@ -293,6 +306,8 @@ impl Core {
|
|||
}
|
||||
|
||||
self.N_cycle16(sb, self.pc + 2);
|
||||
|
||||
CpuAction::AdvancePC
|
||||
}
|
||||
|
||||
/// Format 9
|
||||
|
|
@ -300,7 +315,7 @@ impl Core {
|
|||
&mut self,
|
||||
sb: &mut SysBus,
|
||||
insn: ThumbInstruction,
|
||||
) {
|
||||
) -> CpuAction {
|
||||
let rb = insn.raw.bit_range(3..6) as usize;
|
||||
|
||||
let offset = if insn.raw.bit(12) {
|
||||
|
|
@ -317,7 +332,7 @@ impl Core {
|
|||
&mut self,
|
||||
sb: &mut SysBus,
|
||||
insn: ThumbInstruction,
|
||||
) {
|
||||
) -> CpuAction {
|
||||
let rb = insn.raw.bit_range(3..6) as usize;
|
||||
let rd = (insn.raw & 0b111) as usize;
|
||||
let base = self.gpr[rb] as i32;
|
||||
|
|
@ -332,10 +347,12 @@ impl Core {
|
|||
self.N_cycle16(sb, addr);
|
||||
}
|
||||
self.N_cycle16(sb, self.pc + 2);
|
||||
|
||||
CpuAction::AdvancePC
|
||||
}
|
||||
|
||||
/// Format 11
|
||||
fn exec_thumb_ldr_str_sp(&mut self, sb: &mut SysBus, insn: ThumbInstruction) {
|
||||
fn exec_thumb_ldr_str_sp(&mut self, sb: &mut SysBus, insn: ThumbInstruction) -> CpuAction {
|
||||
let addr = self.gpr[REG_SP] + (insn.word8() as Addr);
|
||||
let rd = insn.raw.bit_range(8..11) as usize;
|
||||
if insn.is_load() {
|
||||
|
|
@ -348,6 +365,8 @@ impl Core {
|
|||
self.N_cycle16(sb, addr);
|
||||
}
|
||||
self.N_cycle16(sb, self.pc + 2);
|
||||
|
||||
CpuAction::AdvancePC
|
||||
}
|
||||
|
||||
/// Format 12
|
||||
|
|
@ -355,7 +374,7 @@ impl Core {
|
|||
&mut self,
|
||||
sb: &mut SysBus,
|
||||
insn: ThumbInstruction,
|
||||
) {
|
||||
) -> CpuAction {
|
||||
let rd = insn.raw.bit_range(8..11) as usize;
|
||||
let result = if insn.flag(ThumbInstruction::FLAG_SP) {
|
||||
self.gpr[REG_SP] + (insn.word8() as Addr)
|
||||
|
|
@ -364,19 +383,25 @@ impl Core {
|
|||
};
|
||||
self.gpr[rd] = result;
|
||||
self.S_cycle16(sb, self.pc + 2);
|
||||
|
||||
CpuAction::AdvancePC
|
||||
}
|
||||
|
||||
/// Format 13
|
||||
fn exec_thumb_add_sp(&mut self, sb: &mut SysBus, insn: ThumbInstruction) {
|
||||
fn exec_thumb_add_sp(&mut self, sb: &mut SysBus, insn: ThumbInstruction) -> CpuAction {
|
||||
let op1 = self.gpr[REG_SP] as i32;
|
||||
let op2 = insn.sword7();
|
||||
|
||||
self.gpr[REG_SP] = op1.wrapping_add(op2) as u32;
|
||||
self.S_cycle16(sb, self.pc + 2);
|
||||
|
||||
CpuAction::AdvancePC
|
||||
}
|
||||
|
||||
/// Format 14
|
||||
fn exec_thumb_push_pop(&mut self, sb: &mut SysBus, insn: ThumbInstruction) {
|
||||
fn exec_thumb_push_pop(&mut self, sb: &mut SysBus, insn: ThumbInstruction) -> CpuAction {
|
||||
let mut result = CpuAction::AdvancePC;
|
||||
|
||||
// (From GBATEK) Execution Time: nS+1N+1I (POP), (n+1)S+2N+1I (POP PC), or (n-1)S+2N (PUSH).
|
||||
let is_pop = insn.is_load();
|
||||
let pc_lr_flag = insn.flag(ThumbInstruction::FLAG_R);
|
||||
|
|
@ -398,7 +423,7 @@ impl Core {
|
|||
if pc_lr_flag {
|
||||
pop(self, sb, REG_PC);
|
||||
self.pc = self.pc & !1;
|
||||
self.flush_pipeline16(sb);
|
||||
result = CpuAction::FlushPipeline;
|
||||
}
|
||||
self.S_cycle16(sb, self.pc + 2);
|
||||
} else {
|
||||
|
|
@ -417,10 +442,13 @@ impl Core {
|
|||
}
|
||||
}
|
||||
|
||||
result
|
||||
}
|
||||
|
||||
/// Format 15
|
||||
fn exec_thumb_ldm_stm(&mut self, sb: &mut SysBus, insn: ThumbInstruction) {
|
||||
fn exec_thumb_ldm_stm(&mut self, sb: &mut SysBus, insn: ThumbInstruction) -> CpuAction {
|
||||
let mut result = CpuAction::AdvancePC;
|
||||
|
||||
// (From GBATEK) Execution Time: nS+1N+1I (POP), (n+1)S+2N+1I (POP PC), or (n-1)S+2N (PUSH).
|
||||
|
||||
let rb = insn.raw.bit_range(8..11) as usize;
|
||||
|
|
@ -482,7 +510,7 @@ impl Core {
|
|||
if is_load {
|
||||
let val = sb.read_32(addr);
|
||||
self.set_reg(REG_PC, val & !1);
|
||||
self.flush_pipeline16(sb);
|
||||
result = CpuAction::FlushPipeline;
|
||||
} else {
|
||||
sb.write_32(addr, self.pc + 2);
|
||||
}
|
||||
|
|
@ -490,6 +518,7 @@ impl Core {
|
|||
self.gpr[base_reg] = addr + align_preserve;
|
||||
}
|
||||
|
||||
result
|
||||
}
|
||||
|
||||
/// Format 16
|
||||
|
|
@ -497,14 +526,15 @@ impl Core {
|
|||
&mut self,
|
||||
sb: &mut SysBus,
|
||||
insn: ThumbInstruction,
|
||||
) {
|
||||
) -> CpuAction {
|
||||
if !self.check_arm_cond(insn.cond()) {
|
||||
self.S_cycle16(sb, self.pc + 2);
|
||||
CpuAction::AdvancePC
|
||||
} else {
|
||||
let offset = insn.bcond_offset();
|
||||
self.S_cycle16(sb, self.pc);
|
||||
self.pc = (self.pc as i32).wrapping_add(offset) as u32;
|
||||
self.flush_pipeline16(sb);
|
||||
CpuAction::FlushPipeline
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -513,17 +543,20 @@ impl Core {
|
|||
&mut self,
|
||||
sb: &mut SysBus,
|
||||
_insn: ThumbInstruction,
|
||||
) {
|
||||
) -> CpuAction {
|
||||
self.N_cycle16(sb, self.pc);
|
||||
self.exception(sb, Exception::SoftwareInterrupt, self.pc - 2);
|
||||
|
||||
CpuAction::FlushPipeline
|
||||
}
|
||||
|
||||
/// Format 18
|
||||
fn exec_thumb_branch(&mut self, sb: &mut SysBus, insn: ThumbInstruction) {
|
||||
fn exec_thumb_branch(&mut self, sb: &mut SysBus, insn: ThumbInstruction) -> CpuAction {
|
||||
let offset = ((insn.offset11() << 21) >> 20) as i32;
|
||||
self.pc = (self.pc as i32).wrapping_add(offset) as u32;
|
||||
self.S_cycle16(sb, self.pc);
|
||||
self.flush_pipeline16(sb);
|
||||
|
||||
CpuAction::FlushPipeline
|
||||
}
|
||||
|
||||
/// Format 19
|
||||
|
|
@ -531,7 +564,7 @@ impl Core {
|
|||
&mut self,
|
||||
sb: &mut SysBus,
|
||||
insn: ThumbInstruction,
|
||||
) {
|
||||
) -> CpuAction {
|
||||
let mut off = insn.offset11();
|
||||
if insn.flag(ThumbInstruction::FLAG_LOW_OFFSET) {
|
||||
self.S_cycle16(sb, self.pc);
|
||||
|
|
@ -540,15 +573,17 @@ impl Core {
|
|||
self.pc = ((self.gpr[REG_LR] & !1) as i32).wrapping_add(off) as u32;
|
||||
self.gpr[REG_LR] = next_pc;
|
||||
|
||||
self.flush_pipeline16(sb);
|
||||
CpuAction::FlushPipeline
|
||||
} else {
|
||||
off = (off << 21) >> 9;
|
||||
self.gpr[REG_LR] = (self.pc as i32).wrapping_add(off) as u32;
|
||||
self.S_cycle16(sb, self.pc);
|
||||
|
||||
CpuAction::AdvancePC
|
||||
}
|
||||
}
|
||||
|
||||
pub fn exec_thumb(&mut self, bus: &mut SysBus, insn: ThumbInstruction) {
|
||||
pub fn exec_thumb(&mut self, bus: &mut SysBus, insn: ThumbInstruction) -> CpuAction {
|
||||
match insn.fmt {
|
||||
ThumbFormat::MoveShiftedReg => self.exec_thumb_move_shifted_reg(bus, insn),
|
||||
ThumbFormat::AddSub => self.exec_thumb_add_sub(bus, insn),
|
||||
|
|
|
|||
Reference in a new issue