[perf] arm: Improve performance with barrel shifter.
Instead of using a struct member to hold the last barrel shifter carry output, which is expansive as it needs to be saved/loaded from memory, I now pass the carry around as an INOUT parameter.
Using perf anotate really shows high perctile of samples being spent on reading/writing `self.bs_carry_out`
Since this is a rather "surgical" changeset, I have made sure to run it against eggvance test suite, mGBA test suite and some games as well.
I actually saw better improvements than what the benchmark measured, but 7% is decent enough :)
```
run_60_frames time: [180.18 ms 180.45 ms 180.77 ms]
change: [-7.2464% -6.9081% -6.6324%] (p = 0.00 < 0.05)
Performance has improved.
```
Former-commit-id: 7cd7105a07aa0b78cab9dc8bbae3682b02b7ab7c
Former-commit-id: c68514beb3fa6c34f5f65544acbead21e527dbb0
This commit is contained in:
Michel Heily
parent
caf89d8532
commit
20506091cc
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@ -111,66 +111,59 @@ impl BarrelShifterValue {
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}
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impl<I: MemoryInterface> Core<I> {
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pub fn lsl(&mut self, val: u32, amount: u32, carry_in: bool) -> u32 {
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pub fn lsl(&mut self, val: u32, amount: u32, carry: &mut bool) -> u32 {
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match amount {
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0 => {
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self.bs_carry_out = carry_in;
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val
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}
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0 => val,
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x if x < 32 => {
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self.bs_carry_out = val.wrapping_shr(32 - x) & 1 == 1;
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*carry = val.wrapping_shr(32 - x) & 1 == 1;
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val << x
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}
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32 => {
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self.bs_carry_out = val & 1 == 1;
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*carry = val & 1 == 1;
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0
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}
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_ => {
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self.bs_carry_out = false;
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*carry = false;
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0
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}
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}
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}
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pub fn lsr(&mut self, val: u32, amount: u32, carry_in: bool, immediate: bool) -> u32 {
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pub fn lsr(&mut self, val: u32, amount: u32, carry: &mut bool, immediate: bool) -> u32 {
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if amount != 0 {
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match amount {
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x if x < 32 => {
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self.bs_carry_out = (val >> (amount - 1) & 1) == 1;
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*carry = (val >> (amount - 1) & 1) == 1;
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val >> amount
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}
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32 => {
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self.bs_carry_out = val.bit(31);
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*carry = val.bit(31);
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0
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}
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_ => {
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self.bs_carry_out = false;
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*carry = false;
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0
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}
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}
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} else if immediate {
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self.bs_carry_out = val.bit(31);
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*carry = val.bit(31);
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0
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} else {
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self.bs_carry_out = carry_in;
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val
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}
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}
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pub fn asr(&mut self, val: u32, amount: u32, carry_in: bool, immediate: bool) -> u32 {
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pub fn asr(&mut self, val: u32, amount: u32, carry: &mut bool, immediate: bool) -> u32 {
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let amount = if immediate && amount == 0 { 32 } else { amount };
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match amount {
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0 => {
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self.bs_carry_out = carry_in;
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val
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}
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0 => val,
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x if x < 32 => {
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self.bs_carry_out = val.wrapping_shr(amount - 1) & 1 == 1;
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*carry = val.wrapping_shr(amount - 1) & 1 == 1;
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(val as i32).wrapping_shr(amount) as u32
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}
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_ => {
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let bit31 = val.bit(31);
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self.bs_carry_out = bit31;
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*carry = bit31;
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if bit31 {
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0xffffffff
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} else {
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@ -180,9 +173,9 @@ impl<I: MemoryInterface> Core<I> {
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}
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}
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pub fn rrx(&mut self, val: u32, carry_in: bool) -> u32 {
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let old_c = carry_in as i32;
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self.bs_carry_out = val & 0b1 != 0;
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pub fn rrx(&mut self, val: u32, carry: &mut bool) -> u32 {
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let old_c = *carry as i32;
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*carry = val & 0b1 != 0;
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(((val as u32) >> 1) as i32 | (old_c << 31)) as u32
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}
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@ -190,14 +183,14 @@ impl<I: MemoryInterface> Core<I> {
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&mut self,
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val: u32,
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amount: u32,
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carry_in: bool,
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carry: &mut bool,
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immediate: bool,
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rrx: bool,
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) -> u32 {
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match amount {
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0 => {
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if immediate & rrx {
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self.rrx(val, carry_in)
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self.rrx(val, carry)
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} else {
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val
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}
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@ -209,7 +202,7 @@ impl<I: MemoryInterface> Core<I> {
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} else {
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val
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};
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self.bs_carry_out = (val as u32).bit(31);
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*carry = (val as u32).bit(31);
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val
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}
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}
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@ -222,12 +215,9 @@ impl<I: MemoryInterface> Core<I> {
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shift: BarrelShiftOpCode,
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val: u32,
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amount: u32,
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carry_in: bool,
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carry: &mut bool,
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immediate: bool,
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) -> u32 {
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// TODO get rid of Core::bs_carry_out field in favour sending the carry as a &mut reference,
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// Forcing calling functions to do something with the carry :
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self.bs_carry_out = carry_in;
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//
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// From GBATEK:
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// Zero Shift Amount (Shift Register by Immediate, with Immediate=0)
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@ -248,10 +238,10 @@ impl<I: MemoryInterface> Core<I> {
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// in the range 1 to 32 and see above.
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//
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match shift {
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BarrelShiftOpCode::LSL => self.lsl(val, amount, carry_in),
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BarrelShiftOpCode::LSR => self.lsr(val, amount, carry_in, immediate),
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BarrelShiftOpCode::ASR => self.asr(val, amount, carry_in, immediate),
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BarrelShiftOpCode::ROR => self.ror(val, amount, carry_in, immediate, true),
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BarrelShiftOpCode::LSL => self.lsl(val, amount, carry),
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BarrelShiftOpCode::LSR => self.lsr(val, amount, carry, immediate),
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BarrelShiftOpCode::ASR => self.asr(val, amount, carry, immediate),
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BarrelShiftOpCode::ROR => self.ror(val, amount, carry, immediate, true),
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}
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}
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@ -261,7 +251,7 @@ impl<I: MemoryInterface> Core<I> {
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bs_op: BarrelShiftOpCode,
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reg: usize,
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rs: usize,
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carry: bool,
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carry: &mut bool,
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) -> u32 {
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let mut val = self.get_reg(reg);
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if reg == REG_PC {
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@ -271,8 +261,7 @@ impl<I: MemoryInterface> Core<I> {
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self.barrel_shift_op(bs_op, val, amount, carry, false)
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}
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pub fn register_shift(&mut self, shift: &ShiftedRegister) -> u32 {
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let carry = self.cpsr.C();
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pub fn register_shift(&mut self, shift: &ShiftedRegister, carry: &mut bool) -> u32 {
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match shift.shift_by {
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ShiftRegisterBy::ByAmount(amount) => {
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let result =
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@ -285,13 +274,13 @@ impl<I: MemoryInterface> Core<I> {
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}
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}
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pub fn get_barrel_shifted_value(&mut self, sval: &BarrelShifterValue) -> u32 {
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pub fn get_barrel_shifted_value(&mut self, sval: &BarrelShifterValue, carry: &mut bool) -> u32 {
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// TODO decide if error handling or panic here
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match sval {
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BarrelShifterValue::ImmediateValue(offset) => *offset as u32,
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BarrelShifterValue::ShiftedRegister(shifted_reg) => {
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let added = (*shifted_reg).added.unwrap_or(true);
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let abs = self.register_shift(shifted_reg) as u32;
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let abs = self.register_shift(shifted_reg, carry) as u32;
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if added {
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abs as u32
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} else {
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@ -93,7 +93,10 @@ impl<I: MemoryInterface> Core<I> {
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if insn.bit(25) {
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let immediate = insn & 0xff;
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let rotate = 2 * insn.bit_range(8..12);
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self.ror(immediate, rotate, self.cpsr.C(), false, true)
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let mut carry = self.cpsr.C();
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let v = self.ror(immediate, rotate, &mut carry, false, true);
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self.cpsr.set_C(carry);
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v
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} else {
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self.get_reg((insn & 0b1111) as usize)
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}
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@ -175,13 +178,12 @@ impl<I: MemoryInterface> Core<I> {
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let mut s_flag = insn.set_cond_flag();
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let opcode = insn.opcode();
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let mut carry = self.cpsr.C();
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let op2 = if insn.bit(25) {
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let immediate = insn & 0xff;
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let rotate = 2 * insn.bit_range(8..12);
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// TODO refactor out
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let bs_carry_in = self.cpsr.C();
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self.bs_carry_out = bs_carry_in;
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self.ror(immediate, rotate, self.cpsr.C(), false, true)
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self.ror(immediate, rotate, &mut carry, false, true)
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} else {
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let reg = insn & 0xf;
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@ -203,7 +205,7 @@ impl<I: MemoryInterface> Core<I> {
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shift_by: shift_by,
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added: None,
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};
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self.register_shift(&shifted_reg)
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self.register_shift(&shifted_reg, &mut carry)
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};
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if rd == REG_PC && s_flag {
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@ -211,9 +213,7 @@ impl<I: MemoryInterface> Core<I> {
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s_flag = false;
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}
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let carry = self.cpsr.C() as u32;
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let alu_res = if s_flag {
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let mut carry = self.bs_carry_out;
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let mut overflow = self.cpsr.V();
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let result = match opcode {
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AND | TST => op1 & op2,
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@ -238,15 +238,16 @@ impl<I: MemoryInterface> Core<I> {
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Some(result)
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}
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} else {
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let c = carry as u32;
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Some(match opcode {
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AND => op1 & op2,
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EOR => op1 ^ op2,
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SUB => op1.wrapping_sub(op2),
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RSB => op2.wrapping_sub(op1),
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ADD => op1.wrapping_add(op2),
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ADC => op1.wrapping_add(op2).wrapping_add(carry),
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SBC => op1.wrapping_sub(op2.wrapping_add(1 - carry)),
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RSC => op2.wrapping_sub(op1.wrapping_add(1 - carry)),
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ADC => op1.wrapping_add(op2).wrapping_add(c),
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SBC => op1.wrapping_sub(op2.wrapping_add(1 - c)),
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RSC => op2.wrapping_sub(op1.wrapping_add(1 - c)),
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ORR => op1 | op2,
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MOV => op2,
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BIC => op1 & (!op2),
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@ -290,7 +291,9 @@ impl<I: MemoryInterface> Core<I> {
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if base_reg == REG_PC {
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addr = self.pc_arm() + 8; // prefetching
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}
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let offset = self.get_barrel_shifted_value(&insn.ldr_str_offset()); // TODO: wrong to use in here
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let mut carry = self.cpsr.C();
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let offset = self.get_barrel_shifted_value(&insn.ldr_str_offset(), &mut carry); // TODO: wrong to use in here
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self.cpsr.set_C(carry);
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let effective_addr = (addr as i32).wrapping_add(offset as i32) as Addr;
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// TODO - confirm this
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@ -350,15 +353,16 @@ impl<I: MemoryInterface> Core<I> {
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}
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pub fn exec_arm_ldr_str_hs_reg(&mut self, insn: u32) -> CpuAction {
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self.ldr_str_hs(
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insn,
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BarrelShifterValue::ShiftedRegister(ShiftedRegister {
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reg: (insn & 0xf) as usize,
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shift_by: ShiftRegisterBy::ByAmount(0),
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bs_op: BarrelShiftOpCode::LSL,
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added: Some(insn.add_offset_flag()),
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}),
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)
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let offset = {
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let added = insn.add_offset_flag();
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let abs = self.get_reg((insn & 0xf) as usize);
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if added {
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abs as u32
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} else {
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(-(abs as i32)) as u32
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}
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};
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self.ldr_str_hs_common(insn, offset)
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}
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pub fn exec_arm_ldr_str_hs_imm(&mut self, insn: u32) -> CpuAction {
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@ -368,11 +372,11 @@ impl<I: MemoryInterface> Core<I> {
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} else {
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(-(offset8 as i32)) as u32
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};
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self.ldr_str_hs(insn, BarrelShifterValue::ImmediateValue(offset8))
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self.ldr_str_hs_common(insn, offset8)
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}
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#[inline(always)]
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pub fn ldr_str_hs(&mut self, insn: u32, offset: BarrelShifterValue) -> CpuAction {
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pub fn ldr_str_hs_common(&mut self, insn: u32, offset: u32) -> CpuAction {
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let mut result = CpuAction::AdvancePC(NonSeq);
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let load = insn.load_flag();
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@ -385,8 +389,6 @@ impl<I: MemoryInterface> Core<I> {
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addr = self.pc_arm() + 8; // prefetching
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}
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let offset = self.get_barrel_shifted_value(&offset);
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// TODO - confirm this
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let old_mode = self.cpsr.mode();
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if !pre_index && writeback {
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@ -83,8 +83,6 @@ pub struct SavedCpuState {
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pub(super) spsr: RegPSR,
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pub(super) banks: BankedRegisters,
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pub(super) bs_carry_out: bool,
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}
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#[derive(Clone, Debug)]
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@ -125,9 +123,6 @@ pub struct Core<I: MemoryInterface> {
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pub cpsr: RegPSR,
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pub(super) spsr: RegPSR,
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// Todo - do I still need this?
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pub(super) bs_carry_out: bool,
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pub(super) banks: BankedRegisters,
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#[cfg(feature = "debugger")]
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@ -146,7 +141,6 @@ impl<I: MemoryInterface> Core<I> {
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cpsr,
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spsr: Default::default(),
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banks: BankedRegisters::default(),
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bs_carry_out: false,
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#[cfg(feature = "debugger")]
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dbg_info: DebuggerInfo::default(),
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@ -167,7 +161,6 @@ impl<I: MemoryInterface> Core<I> {
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banks: state.banks,
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spsr: state.spsr,
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bs_carry_out: state.bs_carry_out,
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pipeline: state.pipeline,
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next_fetch_access: state.next_fetch_access,
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@ -184,7 +177,6 @@ impl<I: MemoryInterface> Core<I> {
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gpr: self.gpr.clone(),
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spsr: self.spsr,
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banks: self.banks.clone(),
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bs_carry_out: self.bs_carry_out,
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pipeline: self.pipeline.clone(),
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next_fetch_access: self.next_fetch_access,
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}
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@ -196,7 +188,6 @@ impl<I: MemoryInterface> Core<I> {
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self.gpr = state.gpr;
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self.spsr = state.spsr;
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self.banks = state.banks;
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self.bs_carry_out = state.bs_carry_out;
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self.pipeline = state.pipeline;
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self.next_fetch_access = state.next_fetch_access;
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}
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|
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@ -1,8 +1,8 @@
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use std::fmt;
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use std::marker::PhantomData;
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use super::InstructionDecoder;
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use super::Addr;
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use super::InstructionDecoder;
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pub struct Disassembler<'a, D>
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where
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|
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@ -134,7 +134,10 @@ impl<I: MemoryInterface> Core<I> {
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if addr & 0x3 != 0 {
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let rotation = (addr & 0x3) << 3;
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let value = self.load_32(addr & !0x3, access);
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self.ror(value, rotation, self.cpsr.C(), false, false)
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let mut carry = self.cpsr.C();
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let v = self.ror(value, rotation, &mut carry, false, false);
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self.cpsr.set_C(carry);
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v
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} else {
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self.load_32(addr, access)
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}
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|
|
@ -146,7 +149,10 @@ impl<I: MemoryInterface> Core<I> {
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if addr & 0x1 != 0 {
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let rotation = (addr & 0x1) << 3;
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let value = self.load_16(addr & !0x1, access);
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self.ror(value as u32, rotation, self.cpsr.C(), false, false)
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let mut carry = self.cpsr.C();
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let v = self.ror(value as u32, rotation, &mut carry, false, false);
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self.cpsr.set_C(carry);
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v
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} else {
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self.load_16(addr, access) as u32
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}
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|
|
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|
|
@ -15,15 +15,16 @@ impl<I: MemoryInterface> Core<I> {
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let rs = insn.bit_range(3..6) as usize;
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let shift_amount = insn.offset5() as u8 as u32;
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let mut carry = self.cpsr.C();
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||||
let op2 = self.barrel_shift_op(
|
||||
insn.format1_op(),
|
||||
self.gpr[rs],
|
||||
shift_amount,
|
||||
self.cpsr.C(),
|
||||
&mut carry,
|
||||
true,
|
||||
);
|
||||
self.gpr[rd] = op2;
|
||||
self.alu_update_flags(op2, false, self.bs_carry_out, self.cpsr.V());
|
||||
self.alu_update_flags(op2, false, carry, self.cpsr.V());
|
||||
|
||||
CpuAction::AdvancePC(Seq)
|
||||
}
|
||||
|
|
@ -95,9 +96,8 @@ impl<I: MemoryInterface> Core<I> {
|
|||
|
||||
macro_rules! shifter_op {
|
||||
($bs_op:expr) => {{
|
||||
let result = self.shift_by_register($bs_op, rd, rs, carry);
|
||||
let result = self.shift_by_register($bs_op, rd, rs, &mut carry);
|
||||
self.idle_cycle();
|
||||
carry = self.bs_carry_out;
|
||||
result
|
||||
}};
|
||||
}
|
||||
|
|
|
|||
|
|
@ -336,7 +336,10 @@ impl EepromController {
|
|||
match (src, dst) {
|
||||
// DMA to EEPROM
|
||||
(_, 0x0d000000..=0x0dffffff) => {
|
||||
debug!("caught eeprom dma transfer src={:#x} dst={:#x} count={}", src, dst, count);
|
||||
debug!(
|
||||
"caught eeprom dma transfer src={:#x} dst={:#x} count={}",
|
||||
src, dst, count
|
||||
);
|
||||
let eeprom_type = match count {
|
||||
// Read(11) + 6bit address + stop bit
|
||||
9 => Eeprom512,
|
||||
|
|
@ -346,7 +349,10 @@ impl EepromController {
|
|||
73 => Eeprom512,
|
||||
// Write(11) + 14bit address + 64bit value + stop bit
|
||||
81 => Eeprom8k,
|
||||
_ => panic!("unexpected bit count ({}) when detecting eeprom size", count)
|
||||
_ => panic!(
|
||||
"unexpected bit count ({}) when detecting eeprom size",
|
||||
count
|
||||
),
|
||||
};
|
||||
info!("detected eeprom type: {:?}", eeprom_type);
|
||||
self.chip.borrow_mut().set_type(eeprom_type);
|
||||
|
|
|
|||
|
|
@ -291,10 +291,7 @@ impl SoundController {
|
|||
self.resampler.in_freq = self.sample_rate;
|
||||
}
|
||||
self.cycles_per_sample = 512 >> resolution;
|
||||
info!(
|
||||
"bias - setting sample frequency to {}hz",
|
||||
self.sample_rate
|
||||
);
|
||||
info!("bias - setting sample frequency to {}hz", self.sample_rate);
|
||||
// TODO this will not affect the currently scheduled sample event
|
||||
}
|
||||
|
||||
|
|
|
|||
Reference in a new issue