From 22933002606ad5966e825879bc4616f7fd47e257 Mon Sep 17 00:00:00 2001
From: Michel Heily <michelheily@gmail.com>
Date: Thu, 4 Jul 2019 02:06:41 +0300
Subject: [PATCH] Add test for the bug fixed on e2a1303

Former-commit-id: 98d0789aaf92a549cbe1b387461fd9acd4d773c0
---
 src/arm7tdmi/arm/mod.rs | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/src/arm7tdmi/arm/mod.rs b/src/arm7tdmi/arm/mod.rs
index 9d86caf..b5f5825 100644
--- a/src/arm7tdmi/arm/mod.rs
+++ b/src/arm7tdmi/arm/mod.rs
@@ -442,6 +442,8 @@ impl ArmInstruction {
 /// All instructions constants were generated using an ARM assembler.
 mod tests {
     use super::*;
+    use crate::arm7tdmi::*;
+    use crate::sysbus::BoxedMemory;
 
     #[test]
     fn test_decode_swi() {
@@ -523,4 +525,30 @@ mod tests {
 
         assert_eq!(format!("{}", decoded), "strteq\tr2, [r4], -r7, asr #8");
     }
+
+    #[test]
+    fn str_pre_index() {
+        // str r4, [sp, 0x10]
+        let decoded = ArmInstruction::decode(0xe58d4010, 0).unwrap();
+        assert_eq!(decoded.fmt, ArmFormat::LDR_STR);
+        assert_eq!(decoded.cond, ArmCond::Always);
+
+        let mut core = Core::new();
+        core.set_reg(4, 0x12345678);
+        core.set_reg(REG_SP, 0);
+
+        let bytes = vec![
+            /*  0: */ 0xaa, 0xbb, 0xcc, 0xdd,
+            /*  4: */ 0xaa, 0xbb, 0xcc, 0xdd,
+            /*  8: */ 0xaa, 0xbb, 0xcc, 0xdd,
+            /*  c: */ 0xaa, 0xbb, 0xcc, 0xdd,
+            /* 10: */ 0xaa, 0xbb, 0xcc, 0xdd,
+        ];
+        let mut mem = BoxedMemory::new(bytes.into_boxed_slice());
+
+        assert_ne!(mem.read_32(core.get_reg(REG_SP) + 0x10), 0x12345678);
+        assert_eq!(core.exec_arm(&mut mem, decoded), Ok(CpuPipelineAction::IncPC));
+        assert_eq!(mem.read_32(core.get_reg(REG_SP) + 0x10), 0x12345678);
+
+    }
 }