diff --git a/src/core/arm7tdmi/arm/exec.rs b/src/core/arm7tdmi/arm/exec.rs
index 3c8a169..6876aa1 100644
--- a/src/core/arm7tdmi/arm/exec.rs
+++ b/src/core/arm7tdmi/arm/exec.rs
@@ -208,9 +208,8 @@ impl Core {
     /// For LDR, add y=1S+1N if Rd=R15.
     fn exec_ldr_str(&mut self, bus: &mut Bus, insn: ArmInstruction) -> CpuExecResult {
         let mut writeback = insn.write_back_flag();
-
         if writeback && insn.rd() == insn.rn() {
-            return Err(CpuError::IllegalInstruction);
+            writeback = false;
         }
 
         let mut addr = self.get_reg(insn.rn());
@@ -266,7 +265,7 @@ impl Core {
     fn exec_ldr_str_hs(&mut self, bus: &mut Bus, insn: ArmInstruction) -> CpuExecResult {
         let mut writeback = insn.write_back_flag();
         if writeback && insn.rd() == insn.rn() {
-            return Err(CpuError::IllegalInstruction);
+            writeback = false;
         }
 
         let mut addr = self.get_reg(insn.rn());