diff --git a/arm7tdmi/src/alu.rs b/arm7tdmi/src/alu.rs
index 06c8e5d..9d0a897 100644
--- a/arm7tdmi/src/alu.rs
+++ b/arm7tdmi/src/alu.rs
@@ -25,29 +25,20 @@ pub enum AluOpCode {
 impl AluOpCode {
     pub fn is_setting_flags(&self) -> bool {
         use AluOpCode::*;
-        match self {
-            TST | TEQ | CMP | CMN => true,
-            _ => false,
-        }
+        matches!(self, TST | TEQ | CMP | CMN)
     }
 
     pub fn is_logical(&self) -> bool {
         use AluOpCode::*;
-        match self {
-            MOV | MVN | ORR | EOR | AND | BIC | TST | TEQ => true,
-            _ => false,
-        }
+        matches!(self, MOV | MVN | ORR | EOR | AND | BIC | TST | TEQ)
     }
     pub fn is_arithmetic(&self) -> bool {
         use AluOpCode::*;
-        match self {
-            ADD | ADC | SUB | SBC | RSB | RSC | CMP | CMN => true,
-            _ => false,
-        }
+        matches!(self, ADD | ADC | SUB | SBC | RSB | RSC | CMP | CMN)
     }
 }
 
-#[derive(Debug, PartialEq, Primitive, Copy, Clone)]
+#[derive(Debug, PartialEq, Eq, Primitive, Copy, Clone)]
 pub enum BarrelShiftOpCode {
     LSL = 0,
     LSR = 1,
@@ -55,13 +46,13 @@ pub enum BarrelShiftOpCode {
     ROR = 3,
 }
 
-#[derive(Debug, PartialEq, Copy, Clone)]
+#[derive(Debug, PartialEq, Eq, Copy, Clone)]
 pub enum ShiftRegisterBy {
     ByAmount(u32),
     ByRegister(usize),
 }
 
-#[derive(Debug, PartialEq, Copy, Clone)]
+#[derive(Debug, PartialEq, Eq, Copy, Clone)]
 pub struct ShiftedRegister {
     pub reg: usize,
     pub shift_by: ShiftRegisterBy,
@@ -71,14 +62,11 @@ pub struct ShiftedRegister {
 
 impl ShiftedRegister {
     pub fn is_shifted_by_reg(&self) -> bool {
-        match self.shift_by {
-            ShiftRegisterBy::ByRegister(_) => true,
-            _ => false,
-        }
+        matches!(self.shift_by, ShiftRegisterBy::ByRegister(_))
     }
 }
 
-#[derive(Debug, PartialEq, Copy, Clone)]
+#[derive(Debug, PartialEq, Eq, Copy, Clone)]
 pub enum BarrelShifterValue {
     ImmediateValue(u32),
     RotatedImmediate(u32, u32),
@@ -285,9 +273,7 @@ impl<I: MemoryInterface> Arm7tdmiCore<I> {
     pub fn register_shift(&mut self, shift: &ShiftedRegister, carry: &mut bool) -> u32 {
         match shift.shift_by {
             ShiftRegisterBy::ByAmount(amount) => {
-                let result =
-                    self.barrel_shift_op(shift.bs_op, self.get_reg(shift.reg), amount, carry, true);
-                result
+                self.barrel_shift_op(shift.bs_op, self.get_reg(shift.reg), amount, carry, true)
             }
             ShiftRegisterBy::ByRegister(rs) => {
                 self.shift_by_register(shift.bs_op, shift.reg, rs, carry)
diff --git a/arm7tdmi/src/arm/exec.rs b/arm7tdmi/src/arm/exec.rs
index 72fd706..417955d 100644
--- a/arm7tdmi/src/arm/exec.rs
+++ b/arm7tdmi/src/arm/exec.rs
@@ -1,4 +1,4 @@
-use crate::bit::BitIndex;
+use bit::BitIndex;
 
 use crate::{
     alu::*,
@@ -36,12 +36,12 @@ impl<I: MemoryInterface> Arm7tdmiCore<I> {
 
     pub fn branch_exchange(&mut self, mut addr: Addr) -> CpuAction {
         if addr.bit(0) {
-            addr = addr & !0x1;
+            addr &= !0x1;
             self.cpsr.set_state(CpuState::THUMB);
             self.pc = addr;
             self.reload_pipeline16();
         } else {
-            addr = addr & !0x3;
+            addr &= !0x3;
             self.cpsr.set_state(CpuState::ARM);
             self.pc = addr;
             self.reload_pipeline32();
@@ -101,7 +101,7 @@ impl<I: MemoryInterface> Arm7tdmiCore<I> {
             mask |= 0xff << 8;
         }
         if c {
-            mask |= 0xff << 0;
+            mask |= 0xff;
         }
 
         match self.cpsr.mode() {
@@ -186,7 +186,7 @@ impl<I: MemoryInterface> Arm7tdmiCore<I> {
             let shifted_reg = ShiftedRegister {
                 reg: reg as usize,
                 bs_op: insn.get_bs_op(),
-                shift_by: shift_by,
+                shift_by,
                 added: None,
             };
             self.register_shift(&shifted_reg, &mut carry)
@@ -335,10 +335,8 @@ impl<I: MemoryInterface> Arm7tdmiCore<I> {
             };
         }
 
-        if !LOAD || base_reg != dest_reg {
-            if !PRE_INDEX || WRITEBACK{
-                self.set_reg(base_reg, effective_addr);
-            }
+        if (!LOAD || base_reg != dest_reg) && (!PRE_INDEX || WRITEBACK) {
+            self.set_reg(base_reg, effective_addr);
         }
 
         if !PRE_INDEX && WRITEBACK {
@@ -444,12 +442,8 @@ impl<I: MemoryInterface> Arm7tdmiCore<I> {
             };
         }
 
-        if !LOAD || base_reg != dest_reg {
-            if !PRE_INDEX {
-                self.set_reg(base_reg, effective_addr);
-            } else if WRITEBACK {
-                self.set_reg(base_reg, effective_addr);
-            }
+        if (!LOAD || base_reg != dest_reg) && (!PRE_INDEX || WRITEBACK) {
+            self.set_reg(base_reg, effective_addr);
         }
 
         result
@@ -554,16 +548,14 @@ impl<I: MemoryInterface> Arm7tdmiCore<I> {
                             } else {
                                 self.get_reg(r)
                             }
+                        } else if first {
+                            old_base
                         } else {
-                            if first {
-                                old_base
+                            let x = rlist_count * 4;
+                            if ascending {
+                                old_base + x
                             } else {
-                                let x = rlist_count * 4;
-                                if ascending {
-                                    old_base + x
-                                } else {
-                                    old_base - x
-                                }
+                                old_base - x
                             }
                         };
 
diff --git a/arm7tdmi/src/arm/mod.rs b/arm7tdmi/src/arm/mod.rs
index f64540b..5f8a378 100644
--- a/arm7tdmi/src/arm/mod.rs
+++ b/arm7tdmi/src/arm/mod.rs
@@ -14,7 +14,7 @@ use num::FromPrimitive;
 
 use std::io;
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum ArmDecodeErrorKind {
     UnknownInstructionFormat,
     DecodedPartDoesNotBelongToInstruction,
@@ -24,7 +24,7 @@ pub enum ArmDecodeErrorKind {
     IoError(io::ErrorKind),
 }
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub struct ArmDecodeError {
     pub kind: ArmDecodeErrorKind,
     pub insn: u32,
@@ -34,15 +34,11 @@ pub struct ArmDecodeError {
 #[allow(dead_code)]
 impl ArmDecodeError {
     fn new(kind: ArmDecodeErrorKind, insn: u32, addr: Addr) -> ArmDecodeError {
-        ArmDecodeError {
-            kind: kind,
-            insn: insn,
-            addr: addr,
-        }
+        ArmDecodeError { kind, insn, addr }
     }
 }
 
-#[derive(Serialize, Deserialize, Debug, Copy, Clone, PartialEq, Primitive)]
+#[derive(Serialize, Deserialize, Debug, Copy, Clone, PartialEq, Eq, Primitive)]
 pub enum ArmCond {
     EQ = 0b0000,
     NE = 0b0001,
@@ -62,7 +58,7 @@ pub enum ArmCond {
     Invalid = 0b1111,
 }
 
-#[derive(Serialize, Deserialize, Debug, Copy, Clone, PartialEq)]
+#[derive(Serialize, Deserialize, Debug, Copy, Clone, PartialEq, Eq)]
 pub enum ArmFormat {
     BranchExchange = 0,
     BranchLink,
@@ -90,33 +86,33 @@ impl From<u32> for ArmFormat {
         use ArmFormat::*;
         if (0x0fff_fff0 & raw) == 0x012f_ff10 {
             BranchExchange
-        } else if (0x0e00_0000 & raw) == 0x0a00_0000 {
+        } else if (0x0E00_0000 & raw) == 0x0A00_0000 {
             BranchLink
-        } else if (0xe000_0010 & raw) == 0x0600_0000 {
+        } else if (0x0E00_0010 & raw) == 0x0600_0000 {
             Undefined
-        } else if (0x0fb0_0ff0 & raw) == 0x0100_0090 {
+        } else if (0x0FB0_0FF0 & raw) == 0x0100_0090 {
             SingleDataSwap
-        } else if (0x0fc0_00f0 & raw) == 0x0000_0090 {
+        } else if (0x0FC0_00F0 & raw) == 0x0000_0090 {
             Multiply
-        } else if (0x0f80_00f0 & raw) == 0x0080_0090 {
+        } else if (0x0F80_00F0 & raw) == 0x0080_0090 {
             MultiplyLong
-        } else if (0x0fbf_0fff & raw) == 0x010f_0000 {
+        } else if (0x0FBF_0FFF & raw) == 0x010F_0000 {
             MoveFromStatus
-        } else if (0x0fbf_fff0 & raw) == 0x0129_f000 {
+        } else if (0x0FBF_FFF0 & raw) == 0x0129_F000 {
             MoveToStatus
-        } else if (0x0dbf_f000 & raw) == 0x0128_f000 {
+        } else if (0x0DBF_F000 & raw) == 0x0128_F000 {
             MoveToFlags
-        } else if (0x0c00_0000 & raw) == 0x0400_0000 {
+        } else if (0x0C00_0000 & raw) == 0x0400_0000 {
             SingleDataTransfer
-        } else if (0x0e40_0F90 & raw) == 0x0000_0090 {
+        } else if (0x0E40_0F90 & raw) == 0x0000_0090 {
             HalfwordDataTransferRegOffset
-        } else if (0x0e40_0090 & raw) == 0x0040_0090 {
+        } else if (0x0E40_0090 & raw) == 0x0040_0090 {
             HalfwordDataTransferImmediateOffset
-        } else if (0x0e00_0000 & raw) == 0x0800_0000 {
+        } else if (0x0E00_0000 & raw) == 0x0800_0000 {
             BlockDataTransfer
-        } else if (0x0f00_0000 & raw) == 0x0f00_0000 {
+        } else if (0x0F00_0000 & raw) == 0x0F00_0000 {
             SoftwareInterrupt
-        } else if (0x0c00_0000 & raw) == 0x0000_0000 {
+        } else if (0x0C00_0000 & raw) == 0x0000_0000 {
             DataProcessing
         } else {
             Undefined
@@ -124,14 +120,14 @@ impl From<u32> for ArmFormat {
     }
 }
 
-#[derive(Debug, PartialEq, Primitive)]
+#[derive(Debug, PartialEq, Eq, Primitive)]
 pub enum ArmHalfwordTransferType {
     UnsignedHalfwords = 0b01,
     SignedByte = 0b10,
     SignedHalfwords = 0b11,
 }
 
-#[derive(Serialize, Deserialize, Debug, Clone, PartialEq)]
+#[derive(Serialize, Deserialize, Debug, Clone, PartialEq, Eq)]
 pub struct ArmInstruction {
     pub fmt: ArmFormat,
     pub raw: u32,
@@ -150,11 +146,7 @@ impl InstructionDecoder for ArmInstruction {
     fn decode(raw: u32, addr: Addr) -> Self {
         let fmt = ArmFormat::from(raw);
 
-        ArmInstruction {
-            fmt: fmt,
-            raw: raw,
-            pc: addr,
-        }
+        ArmInstruction {fmt, raw, pc: addr }
     }
 
     fn decode_from_bytes(bytes: &[u8], addr: Addr) -> Self {
diff --git a/arm7tdmi/src/cpu.rs b/arm7tdmi/src/cpu.rs
index d3a4eb7..033834a 100644
--- a/arm7tdmi/src/cpu.rs
+++ b/arm7tdmi/src/cpu.rs
@@ -166,10 +166,10 @@ impl<I: MemoryInterface> Arm7tdmiCore<I> {
         SavedCpuState {
             cpsr: self.cpsr,
             pc: self.pc,
-            gpr: self.gpr.clone(),
+            gpr: self.gpr,
             spsr: self.spsr,
             banks: self.banks.clone(),
-            pipeline: self.pipeline.clone(),
+            pipeline: self.pipeline,
             next_fetch_access: self.next_fetch_access,
         }
     }
@@ -264,8 +264,8 @@ impl<I: MemoryInterface> Arm7tdmiCore<I> {
         }
     }
 
-    pub fn get_registers(&self) -> [u32; 15] {
-        self.gpr.clone()
+    pub fn copy_registers(&self) -> [u32; 15] {
+        self.gpr
     }
 
     pub(super) fn change_mode(&mut self, old_mode: CpuMode, new_mode: CpuMode) {
@@ -352,7 +352,7 @@ impl<I: MemoryInterface> Arm7tdmiCore<I> {
 
     #[cfg(feature = "debugger")]
     fn debugger_record_step(&mut self, d: DecodedInstruction) {
-        self.dbg.gpr_previous = self.get_registers();
+        self.dbg.gpr_previous = self.copy_registers();
         self.dbg.last_executed = Some(d);
     }
 
@@ -433,12 +433,10 @@ impl<I: MemoryInterface> Arm7tdmiCore<I> {
                 self.pipeline[1] = fetched_now;
                 let cond = ArmCond::from_u8(insn.bit_range(28..32) as u8)
                     .unwrap_or_else(|| unsafe { std::hint::unreachable_unchecked() });
-                if cond != ArmCond::AL {
-                    if !self.check_arm_cond(cond) {
-                        self.advance_arm();
-                        self.next_fetch_access = MemoryAccess::NonSeq;
-                        return;
-                    }
+                if cond != ArmCond::AL && !self.check_arm_cond(cond) {
+                    self.advance_arm();
+                    self.next_fetch_access = MemoryAccess::NonSeq;
+                    return;
                 }
                 match self.step_arm_exec(insn) {
                     CpuAction::AdvancePC(access) => {
@@ -499,7 +497,7 @@ impl<I: MemoryInterface> fmt::Display for Core<I> {
         writeln!(f, "\tGeneral Purpose Registers:")?;
         let reg_normal_style = Style::new().bold();
         let reg_dirty_style = Colour::Black.bold().on(Colour::Yellow);
-        let gpr = self.get_registers();
+        let gpr = self.copy_registers();
         for i in 0..15 {
             let mut reg_name = reg_string(i).to_string();
             reg_name.make_ascii_uppercase();
diff --git a/arm7tdmi/src/disass.rs b/arm7tdmi/src/disass.rs
index bae98e4..c178e78 100644
--- a/arm7tdmi/src/disass.rs
+++ b/arm7tdmi/src/disass.rs
@@ -1,4 +1,5 @@
 use std::fmt;
+use std::fmt::Write;
 use std::marker::PhantomData;
 
 use super::Addr;
@@ -23,7 +24,7 @@ where
         Disassembler {
             base: base as Addr,
             pos: 0,
-            bytes: bytes,
+            bytes,
             word_size: std::mem::size_of::<D::IntType>(),
             instruction_decoder: PhantomData,
         }
@@ -42,14 +43,9 @@ where
 
         let addr = self.base + self.pos as Addr;
         let decoded: D = D::decode_from_bytes(&self.bytes[(self.pos as usize)..], addr);
+        let decoded_raw = decoded.get_raw();
         self.pos += self.word_size;
-        line.push_str(&format!(
-            "{:8x}:\t{:08x} \t{}",
-            addr,
-            decoded.get_raw(),
-            decoded
-        ));
-
+        write!(&mut line, "{addr:8x}:\t{decoded_raw:08x} \t{decoded}").unwrap();
         Some((self.pos as Addr, line))
     }
 }
diff --git a/arm7tdmi/src/exception.rs b/arm7tdmi/src/exception.rs
index 2b2322a..30d316b 100644
--- a/arm7tdmi/src/exception.rs
+++ b/arm7tdmi/src/exception.rs
@@ -2,7 +2,7 @@ use super::memory::MemoryInterface;
 use super::Arm7tdmiCore;
 use super::{CpuMode, CpuState};
 
-#[derive(Debug, Clone, Copy, PartialEq)]
+#[derive(Debug, Clone, Copy, PartialEq, Eq)]
 #[allow(dead_code)]
 /// Models a CPU exception, and maps to the relavnt entry in the exception vector
 pub enum Exception {
diff --git a/arm7tdmi/src/lib.rs b/arm7tdmi/src/lib.rs
index 90952fa..8d3aaf2 100644
--- a/arm7tdmi/src/lib.rs
+++ b/arm7tdmi/src/lib.rs
@@ -3,9 +3,6 @@ extern crate serde;
 
 #[macro_use]
 extern crate enum_primitive_derive;
-use bit;
-use num;
-use num_traits;
 
 use std::fmt;
 
@@ -35,7 +32,7 @@ pub mod registers_consts {
     pub const REG_SP: usize = 13;
 }
 
-#[derive(Serialize, Deserialize, Debug, PartialEq, Clone)]
+#[derive(Serialize, Deserialize, Debug, PartialEq, Eq, Clone)]
 pub enum DecodedInstruction {
     Arm(ArmInstruction),
     Thumb(ThumbInstruction),
@@ -77,7 +74,7 @@ pub fn reg_string<T: Into<usize>>(reg: T) -> &'static str {
     reg_names[reg.into()]
 }
 
-#[derive(Debug, PartialEq, Primitive, Copy, Clone)]
+#[derive(Debug, PartialEq, Eq, Primitive, Copy, Clone)]
 #[repr(u8)]
 pub enum CpuState {
     ARM = 0,
@@ -94,7 +91,7 @@ impl fmt::Display for CpuState {
     }
 }
 
-#[derive(Debug, Primitive, Copy, Clone, PartialEq)]
+#[derive(Debug, Primitive, Copy, Clone, PartialEq, Eq)]
 pub enum CpuMode {
     User = 0b10000,
     Fiq = 0b10001,
diff --git a/arm7tdmi/src/memory.rs b/arm7tdmi/src/memory.rs
index bcf9cc9..f3a30dc 100644
--- a/arm7tdmi/src/memory.rs
+++ b/arm7tdmi/src/memory.rs
@@ -28,7 +28,7 @@ impl fmt::Display for MemoryAccess {
     }
 }
 
-#[derive(Debug, PartialEq, Copy, Clone)]
+#[derive(Debug, PartialEq, Eq, Copy, Clone)]
 #[repr(u8)]
 pub enum MemoryAccessWidth {
     MemoryAccess8 = 0,
diff --git a/arm7tdmi/src/psr.rs b/arm7tdmi/src/psr.rs
index 949cadd..d75d78f 100644
--- a/arm7tdmi/src/psr.rs
+++ b/arm7tdmi/src/psr.rs
@@ -3,8 +3,8 @@ use std::fmt;
 
 use serde::{Deserialize, Serialize};
 
-use crate::bit::BitIndex;
-use crate::num::FromPrimitive;
+use bit::BitIndex;
+use num::FromPrimitive;
 
 use super::{CpuMode, CpuState};
 
diff --git a/arm7tdmi/src/thumb/exec.rs b/arm7tdmi/src/thumb/exec.rs
index 33e8fca..93cb02d 100644
--- a/arm7tdmi/src/thumb/exec.rs
+++ b/arm7tdmi/src/thumb/exec.rs
@@ -428,7 +428,7 @@ impl<I: MemoryInterface> Arm7tdmiCore<I> {
             }
             if FLAG_R {
                 pop!(REG_PC);
-                self.pc = self.pc & !1;
+                self.pc &= !1;
                 result = CpuAction::PipelineFlushed;
                 self.reload_pipeline16();
             }
@@ -482,16 +482,12 @@ impl<I: MemoryInterface> Arm7tdmiCore<I> {
                     if rlist.bit(r) {
                         let v = if r != RB {
                             self.gpr[r]
-                        } else {
-                            if first {
-                                addr
-                            } else {
-                                addr + (rlist.count_ones() - 1) * 4
-                            }
-                        };
-                        if first {
+                        } else if first {
                             first = false;
-                        }
+                            addr
+                        } else {
+                            addr + (rlist.count_ones() - 1) * 4
+                        };
                         self.store_32(addr, v, access);
                         access = Seq;
                         addr += 4;
@@ -559,7 +555,7 @@ impl<I: MemoryInterface> Arm7tdmiCore<I> {
     ) -> CpuAction {
         let mut off = insn.offset11();
         if FLAG_LOW_OFFSET {
-            off = off << 1;
+            off <<= 1;
             let next_pc = (self.pc - 2) | 1;
             self.pc = ((self.gpr[REG_LR] & !1) as i32).wrapping_add(off) as u32;
             self.gpr[REG_LR] = next_pc;
diff --git a/arm7tdmi/src/thumb/mod.rs b/arm7tdmi/src/thumb/mod.rs
index 35bfc29..227620b 100644
--- a/arm7tdmi/src/thumb/mod.rs
+++ b/arm7tdmi/src/thumb/mod.rs
@@ -10,7 +10,7 @@ use num::FromPrimitive;
 pub mod disass;
 pub mod exec;
 
-#[derive(Serialize, Deserialize, Debug, Copy, Clone, PartialEq)]
+#[derive(Serialize, Deserialize, Debug, Copy, Clone, PartialEq, Eq)]
 pub enum ThumbFormat {
     /// Format 1
     MoveShiftedReg,
@@ -102,7 +102,7 @@ impl From<u16> for ThumbFormat {
     }
 }
 
-#[derive(Serialize, Deserialize, Debug, Clone, PartialEq)]
+#[derive(Serialize, Deserialize, Debug, Clone, PartialEq, Eq)]
 pub struct ThumbInstruction {
     pub fmt: ThumbFormat,
     pub raw: u16,
@@ -134,7 +134,7 @@ impl InstructionDecoder for ThumbInstruction {
     }
 }
 
-#[derive(Debug, Primitive, PartialEq)]
+#[derive(Debug, Primitive, PartialEq, Eq)]
 pub enum OpFormat3 {
     MOV = 0,
     CMP = 1,
@@ -153,7 +153,7 @@ impl From<OpFormat3> for AluOpCode {
     }
 }
 
-#[derive(Debug, Primitive, PartialEq)]
+#[derive(Debug, Primitive, PartialEq, Eq)]
 pub enum OpFormat5 {
     ADD = 0,
     CMP = 1,
@@ -161,7 +161,7 @@ pub enum OpFormat5 {
     BX = 3,
 }
 
-#[derive(Debug, Primitive, PartialEq)]
+#[derive(Debug, Primitive, PartialEq, Eq)]
 pub enum ThumbAluOps {
     AND = 0b0000,
     EOR = 0b0001,
@@ -184,17 +184,11 @@ pub enum ThumbAluOps {
 impl ThumbAluOps {
     pub fn is_setting_flags(&self) -> bool {
         use ThumbAluOps::*;
-        match self {
-            TST | CMP | CMN => true,
-            _ => false,
-        }
+        matches!(self, TST | CMP | CMN)
     }
     pub fn is_arithmetic(&self) -> bool {
         use ThumbAluOps::*;
-        match self {
-            ADC | SBC | NEG | CMP | CMN => true,
-            _ => false,
-        }
+        matches!(self, ADC | SBC | NEG | CMP | CMN)
     }
 }