diff --git a/core/src/dma.rs b/core/src/dma.rs
index e6e0dd6..c2d4c96 100644
--- a/core/src/dma.rs
+++ b/core/src/dma.rs
@@ -88,14 +88,14 @@ impl DmaChannel {
         let timing = ctrl.timing();
         let mut start_immediately = false;
         if ctrl.is_enabled() && !self.ctrl.is_enabled() {
-            trace!(
-                "DMA{} enabled! timing={} src={:#x} dst={:#x} cnt={}",
-                self.id,
-                timing,
-                self.src,
-                self.dst,
-                self.wc
-            );
+            // trace!(
+            //     "DMA{} enabled! timing={} src={:#x} dst={:#x} cnt={}",
+            //     self.id,
+            //     timing,
+            //     self.src,
+            //     self.dst,
+            //     self.wc
+            // );
             self.running = true;
             start_immediately = timing == 0;
             self.internal.src_addr = self.src;
diff --git a/core/src/iodev.rs b/core/src/iodev.rs
index cc9d811..e482601 100644
--- a/core/src/iodev.rs
+++ b/core/src/iodev.rs
@@ -131,6 +131,13 @@ impl Bus for IoDevices {
             REG_DMA1CNT_H => io.dmac.channels[1].ctrl.0,
             REG_DMA2CNT_H => io.dmac.channels[2].ctrl.0,
             REG_DMA3CNT_H => io.dmac.channels[3].ctrl.0,
+            // Even though these registers are write only,
+            // some games may still try to read them.
+            // TODO: should this be treated as an open-bus read?
+            REG_DMA0CNT_L => 0,
+            REG_DMA1CNT_L => 0,
+            REG_DMA2CNT_L => 0,
+            REG_DMA3CNT_L => 0,
 
             REG_WAITCNT => io.waitcnt.0,