diff --git a/src/core/arm7tdmi/cpu.rs b/src/core/arm7tdmi/cpu.rs
index 43b4b2b..bee4ce5 100644
--- a/src/core/arm7tdmi/cpu.rs
+++ b/src/core/arm7tdmi/cpu.rs
@@ -238,41 +238,48 @@ impl Core {
     }
 
     #[allow(non_snake_case)]
+    #[inline(always)]
     pub(super) fn S_cycle32(&mut self, sb: &SysBus, addr: u32) {
         self.cycles += 1;
         self.cycles += sb.get_cycles(addr, Seq + MemoryAccess32);
     }
 
     #[allow(non_snake_case)]
+    #[inline(always)]
     pub(super) fn S_cycle16(&mut self, sb: &SysBus, addr: u32) {
         self.cycles += 1;
         self.cycles += sb.get_cycles(addr, Seq + MemoryAccess16);
     }
 
     #[allow(non_snake_case)]
+    #[inline(always)]
     pub(super) fn S_cycle8(&mut self, sb: &SysBus, addr: u32) {
         self.cycles += 1;
         self.cycles += sb.get_cycles(addr, Seq + MemoryAccess8);
     }
 
     #[allow(non_snake_case)]
+    #[inline(always)]
     pub(super) fn N_cycle32(&mut self, sb: &SysBus, addr: u32) {
         self.cycles += 1;
         self.cycles += sb.get_cycles(addr, NonSeq + MemoryAccess32);
     }
 
     #[allow(non_snake_case)]
+    #[inline(always)]
     pub(super) fn N_cycle16(&mut self, sb: &SysBus, addr: u32) {
         self.cycles += 1;
         self.cycles += sb.get_cycles(addr, NonSeq + MemoryAccess16);
     }
 
     #[allow(non_snake_case)]
+    #[inline(always)]
     pub(super) fn N_cycle8(&mut self, sb: &SysBus, addr: u32) {
         self.cycles += 1;
         self.cycles += sb.get_cycles(addr, NonSeq + MemoryAccess8);
     }
 
+    #[inline]
     pub(super) fn check_arm_cond(&self, cond: ArmCond) -> bool {
         use ArmCond::*;
         match cond {
@@ -322,7 +329,7 @@ impl Core {
         }
     }
 
-    #[inline]
+    #[inline(always)]
     pub fn reload_pipeline16(&mut self, sb: &mut SysBus) {
         self.pipeline[0] = sb.read_16(self.pc) as u32;
         self.N_cycle16(sb, self.pc);
@@ -332,7 +339,7 @@ impl Core {
         self.advance_thumb();
     }
 
-    #[inline]
+    #[inline(always)]
     pub fn reload_pipeline32(&mut self, sb: &mut SysBus) {
         self.pipeline[0] = sb.read_32(self.pc);
         self.N_cycle16(sb, self.pc);
diff --git a/src/core/sysbus.rs b/src/core/sysbus.rs
index 519dc91..ae29c3d 100644
--- a/src/core/sysbus.rs
+++ b/src/core/sysbus.rs
@@ -208,6 +208,7 @@ impl SysBus {
         }
     }
 
+    #[inline(always)]
     pub fn get_cycles(&self, addr: Addr, access: MemoryAccess) -> usize {
         let nonseq_cycles = [4, 3, 2, 8];
         let seq_cycles = [2, 1];