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core: arm7tdmi: optimization: split flush_pipeline to arm and thumb

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Reduces an if check


Former-commit-id: 4380c54f86238ef8818356f4593f59277f055fa6
This commit is contained in:
Michel Heily 2020-01-01 01:21:33 +02:00
parent 0872ff650a
commit 36cf4e62ce
4 changed files with 24 additions and 26 deletions
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14
src/core/arm7tdmi/arm/exec.rs
View file

@ -44,7 +44,7 @@ impl Core {
}
self.pc = (self.pc as i32).wrapping_add(insn.branch_offset()) as u32 & !1;
self.flush_pipeline(sb);
self.flush_pipeline32(sb);
Ok(())
}
@ -63,7 +63,7 @@ impl Core {
}
self.pc = addr;
self.flush_pipeline(sb); // +1S+1N
self.flush_pipeline32(sb); // +1S+1N
Ok(())
}
@ -258,7 +258,7 @@ impl Core {
if let Some(result) = alu_res {
if reg_rd == REG_PC {
self.flush_pipeline(sb);
self.flush_pipeline32(sb);
}
self.set_reg(reg_rd, result as u32);
}
@ -306,7 +306,7 @@ impl Core {
self.add_cycle();
if insn.rd() == REG_PC {
self.flush_pipeline(sb);
self.flush_pipeline32(sb);
}
} else {
let value = if insn.rd() == REG_PC {
@ -374,7 +374,7 @@ impl Core {
self.add_cycle();
if insn.rd() == REG_PC {
self.flush_pipeline(sb);
self.flush_pipeline32(sb);
}
} else {
let value = if insn.rd() == REG_PC {
@ -459,7 +459,7 @@ impl Core {
if psr_transfer {
self.transfer_spsr_mode();
}
self.flush_pipeline(sb);
self.flush_pipeline32(sb);
}
if !full {
@ -504,7 +504,7 @@ impl Core {
if is_load {
let val = self.ldr_word(addr as u32, sb);
self.set_reg(REG_PC, val & !3);
self.flush_pipeline(sb);
self.flush_pipeline32(sb);
} else {
self.write_32(addr as u32, self.pc + 4, sb);
}

20
src/core/arm7tdmi/cpu.rs
View file

@ -367,18 +367,16 @@ impl Core {
Ok(())
}
pub(super) fn flush_pipeline(&mut self, sb: &mut SysBus) {
pub(super) fn flush_pipeline16(&mut self, sb: &mut SysBus) {
self.pipeline_state = PipelineState::Refill1;
match self.cpsr.state() {
CpuState::ARM => {
self.N_cycle32(sb, self.pc);
self.S_cycle32(sb, self.pc + 4);
}
CpuState::THUMB => {
self.N_cycle16(sb, self.pc);
self.S_cycle16(sb, self.pc + 2);
}
}
self.N_cycle16(sb, self.pc);
self.S_cycle16(sb, self.pc + 2);
}
pub(super) fn flush_pipeline32(&mut self, sb: &mut SysBus) {
self.pipeline_state = PipelineState::Refill1;
self.N_cycle32(sb, self.pc);
self.S_cycle32(sb, self.pc + 4);
}
fn trace_opcode(&self, insn: u32) {

2
src/core/arm7tdmi/exception.rs
View file

@ -58,7 +58,7 @@ impl Core {
// Set PC to vector address
self.pc = e as u32;
self.flush_pipeline(sb);
self.flush_pipeline32(sb);
}
pub fn irq(&mut self, sb: &mut SysBus) {

14
src/core/arm7tdmi/thumb/exec.rs
View file

@ -183,7 +183,7 @@ impl Core {
OpFormat5::ADD => {
self.set_reg(dst_reg, op1.wrapping_add(op2));
if dst_reg == REG_PC {
self.flush_pipeline(sb);
self.flush_pipeline16(sb);
}
}
OpFormat5::CMP => {
@ -195,7 +195,7 @@ impl Core {
OpFormat5::MOV => {
self.set_reg(dst_reg, op2 as u32);
if dst_reg == REG_PC {
self.flush_pipeline(sb);
self.flush_pipeline16(sb);
}
}
}
@ -409,7 +409,7 @@ impl Core {
if pc_lr_flag {
pop(self, sb, REG_PC);
self.pc = self.pc & !1;
self.flush_pipeline(sb);
self.flush_pipeline16(sb);
}
self.S_cycle16(sb, self.pc + 2);
} else {
@ -481,7 +481,7 @@ impl Core {
if is_load {
let val = self.ldr_word(addr, sb);
self.set_reg(REG_PC, val & !1);
self.flush_pipeline(sb);
self.flush_pipeline16(sb);
} else {
self.write_32(addr, self.pc + 2, sb);
}
@ -507,7 +507,7 @@ impl Core {
let offset = insn.bcond_offset();
self.S_cycle16(sb, self.pc);
self.pc = (self.pc as i32).wrapping_add(offset) as u32;
self.flush_pipeline(sb);
self.flush_pipeline16(sb);
Ok(())
}
}
@ -516,7 +516,7 @@ impl Core {
let offset = ((insn.offset11() << 21) >> 20) as i32;
self.pc = (self.pc as i32).wrapping_add(offset) as u32;
self.S_cycle16(sb, self.pc);
self.flush_pipeline(sb);
self.flush_pipeline16(sb);
Ok(())
}
@ -533,7 +533,7 @@ impl Core {
self.pc = ((self.gpr[REG_LR] & !1) as i32).wrapping_add(off) as u32;
self.gpr[REG_LR] = next_pc;
self.flush_pipeline(sb);
self.flush_pipeline16(sb);
Ok(())
} else {
off = (off << 21) >> 9;