From 4011911cca83c8e8c5853a788d2be5f8410b3757 Mon Sep 17 00:00:00 2001 From: Michel Heily Date: Wed, 3 Jul 2019 01:22:36 +0300 Subject: [PATCH] Pass around "Bus" instead of "SysBus" Former-commit-id: c20dae7dd3ddcb3bd8f671a16fd67a241bd6c459 --- src/arm7tdmi/arm/exec.rs | 14 +++++++------- src/arm7tdmi/cpu.rs | 10 +++++----- src/arm7tdmi/thumb/exec.rs | 4 ++-- src/sysbus.rs | 4 ++-- 4 files changed, 16 insertions(+), 16 deletions(-) diff --git a/src/arm7tdmi/arm/exec.rs b/src/arm7tdmi/arm/exec.rs index 3453bdb..8427968 100644 --- a/src/arm7tdmi/arm/exec.rs +++ b/src/arm7tdmi/arm/exec.rs @@ -13,7 +13,7 @@ use super::{ }; impl Core { - pub fn exec_arm(&mut self, sysbus: &mut SysBus, insn: ArmInstruction) -> CpuExecResult { + pub fn exec_arm(&mut self, sysbus: &mut Bus, insn: ArmInstruction) -> CpuExecResult { if !self.check_arm_cond(insn.cond) { self.add_cycles( insn.pc + (self.word_size() as u32), @@ -41,7 +41,7 @@ impl Core { /// Cycles 2S+1N fn exec_b_bl( &mut self, - sysbus: &mut SysBus, + sysbus: &mut Bus, insn: ArmInstruction, ) -> CpuResult { if insn.link_flag() { @@ -67,7 +67,7 @@ impl Core { /// Cycles 2S+1N fn exec_bx( &mut self, - sysbus: &mut SysBus, + sysbus: &mut Bus, insn: ArmInstruction, ) -> CpuResult { let rn = self.get_reg(insn.rn()); @@ -95,7 +95,7 @@ impl Core { fn exec_swi( &mut self, - _sysbus: &mut SysBus, + _sysbus: &mut Bus, _insn: ArmInstruction, ) -> CpuResult { self.exception(Exception::SoftwareInterrupt); @@ -104,7 +104,7 @@ impl Core { fn exec_msr_reg( &mut self, - sysbus: &mut SysBus, + sysbus: &mut Bus, insn: ArmInstruction, ) -> CpuResult { let new_psr = RegPSR::new(self.get_reg(insn.rm())); @@ -202,7 +202,7 @@ impl Core { /// Add x=1I cycles if Op2 shifted-by-register. Add y=1S+1N cycles if Rd=R15. fn exec_data_processing( &mut self, - sysbus: &mut SysBus, + sysbus: &mut Bus, insn: ArmInstruction, ) -> CpuResult { // TODO handle carry flag @@ -287,7 +287,7 @@ impl Core { /// For LDR, add y=1S+1N if Rd=R15. fn exec_ldr_str( &mut self, - sysbus: &mut SysBus, + sysbus: &mut Bus, insn: ArmInstruction, ) -> CpuResult { if insn.write_back_flag() && insn.rd() == insn.rn() { diff --git a/src/arm7tdmi/cpu.rs b/src/arm7tdmi/cpu.rs index 6d493b3..0c8203b 100644 --- a/src/arm7tdmi/cpu.rs +++ b/src/arm7tdmi/cpu.rs @@ -183,7 +183,7 @@ impl Core { self.cycles += 1; } - pub fn add_cycles(&mut self, addr: Addr, sysbus: &SysBus, access: MemoryAccess) { + pub fn add_cycles(&mut self, addr: Addr, sysbus: &Bus, access: MemoryAccess) { self.cycles += sysbus.get_cycles(addr, access); } @@ -210,7 +210,7 @@ impl Core { fn step_thumb( &mut self, - sysbus: &mut SysBus, + sysbus: &mut Bus, ) -> CpuResult<(Option, CpuPipelineAction)> { // fetch let new_fetched = sysbus.read_16(self.pc); @@ -244,7 +244,7 @@ impl Core { fn step_arm( &mut self, - sysbus: &mut SysBus, + sysbus: &mut Bus, ) -> CpuResult<(Option, CpuPipelineAction)> { // fetch let new_fetched = sysbus.read_32(self.pc); @@ -278,7 +278,7 @@ impl Core { /// Perform a pipeline step /// If an instruction was executed in this step, return it. - pub fn step(&mut self, sysbus: &mut SysBus) -> CpuResult> { + pub fn step(&mut self, sysbus: &mut Bus) -> CpuResult> { let (executed_instruction, pipeline_action) = match self.cpsr.state() { CpuState::ARM => self.step_arm(sysbus), CpuState::THUMB => self.step_thumb(sysbus), @@ -326,7 +326,7 @@ impl Core { /// A step that returns only once an instruction was executed. /// Returns the address of PC before executing an instruction, /// and the address of the next instruction to be executed; - pub fn step_debugger(&mut self, sysbus: &mut SysBus) -> CpuResult { + pub fn step_debugger(&mut self, sysbus: &mut Bus) -> CpuResult { loop { if let Some(i) = self.step(sysbus)? { return Ok(i); diff --git a/src/arm7tdmi/thumb/exec.rs b/src/arm7tdmi/thumb/exec.rs index 63b8d97..bbfe2ff 100644 --- a/src/arm7tdmi/thumb/exec.rs +++ b/src/arm7tdmi/thumb/exec.rs @@ -1,9 +1,9 @@ -use super::super::super::sysbus::SysBus; use super::super::cpu::{Core, CpuExecResult}; use super::ThumbInstruction; +use crate::arm7tdmi::bus::Bus; impl Core { - pub fn exec_thumb(&mut self, sysbus: &mut SysBus, insn: ThumbInstruction) -> CpuExecResult { + pub fn exec_thumb(&mut self, sysbus: &mut Bus, insn: ThumbInstruction) -> CpuExecResult { unimplemented!("thumb not implemented {:#}", insn) } } diff --git a/src/sysbus.rs b/src/sysbus.rs index c56db7c..00dc3b8 100644 --- a/src/sysbus.rs +++ b/src/sysbus.rs @@ -92,7 +92,7 @@ impl SysBus { } } - fn map(&self, addr: Addr) -> &impl Bus { + fn map(&self, addr: Addr) -> & Bus { match addr as usize { 0x0000_0000...0x0000_3fff => &self.bios, 0x0200_0000...0x0203_ffff => &self.onboard_work_ram, @@ -107,7 +107,7 @@ impl SysBus { } /// TODO proc-macro for generating this function - fn map_mut(&mut self, addr: Addr) -> &mut impl Bus { + fn map_mut(&mut self, addr: Addr) -> &mut Bus { match addr as usize { 0x0000_0000...0x0000_3fff => &mut self.bios, 0x0200_0000...0x0203_ffff => &mut self.onboard_work_ram,