arm: do const-generics for HalfwordDataTransfer*
Former-commit-id: 891fd23bef3a4ecc7fe5a4012456d51fc91f8601 Former-commit-id: 431ac09cbf73078988d6400c6320a7fdadceef1a
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@ -272,10 +272,32 @@ fn arm_decode(i: u32) -> (&'static str, String) {
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_ => None,
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};
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result.unwrap_or_else(|| {
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if let Some(result) = result {
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result
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} else {
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match (i.ibit(25), i.ibit(22), i.ibit(7), i.ibit(4)) {
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(0, 0, 1, 1) => ("HalfwordDataTransferRegOffset", String::from("exec_arm_ldr_str_hs_reg")),
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(0, 1, 1, 1) => ("HalfwordDataTransferImmediateOffset", String::from("exec_arm_ldr_str_hs_imm")),
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(0, 0, 1, 1) => (
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"HalfwordDataTransferRegOffset",
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format!(
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"exec_arm_ldr_str_hs_reg::<{HS}, {LOAD}, {WRITEBACK}, {PRE_INDEX}, {ADD}>",
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HS = (i & 0b1100000) >> 5,
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LOAD = i.bit(20),
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WRITEBACK = i.bit(21),
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ADD = i.bit(23),
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PRE_INDEX = i.bit(24),
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),
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),
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(0, 1, 1, 1) => (
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"HalfwordDataTransferImmediateOffset",
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format!(
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"exec_arm_ldr_str_hs_imm::<{HS}, {LOAD}, {WRITEBACK}, {PRE_INDEX}, {ADD}>",
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HS = (i & 0b1100000) >> 5,
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LOAD = i.bit(20),
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WRITEBACK = i.bit(21),
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ADD = i.bit(23),
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PRE_INDEX = i.bit(24)
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),
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),
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_ => {
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let set_cond_flags = i.bit(20);
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// PSR Transfers are encoded as a subset of Data Processing,
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@ -297,7 +319,7 @@ fn arm_decode(i: u32) -> (&'static str, String) {
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}
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}
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}
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})
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}
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}
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0b01 => {
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match (i.bit(25), i.bit(4)) {
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@ -373,36 +373,53 @@ impl<I: MemoryInterface> Core<I> {
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result
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}
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pub fn exec_arm_ldr_str_hs_reg(&mut self, insn: u32) -> CpuAction {
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let offset = {
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let added = insn.add_offset_flag();
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let abs = self.get_reg((insn & 0xf) as usize);
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if added {
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abs as u32
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} else {
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(-(abs as i32)) as u32
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}
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};
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self.ldr_str_hs_common(insn, offset)
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pub fn exec_arm_ldr_str_hs_reg<
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const HS: u8,
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const LOAD: bool,
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const WRITEBACK: bool,
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const PRE_INDEX: bool,
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const ADD: bool,
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>(
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&mut self,
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insn: u32,
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) -> CpuAction {
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let offset = self.get_reg((insn & 0xf) as usize);
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self.ldr_str_hs_common::<HS, LOAD, WRITEBACK, PRE_INDEX, ADD>(insn, offset)
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}
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pub fn exec_arm_ldr_str_hs_imm(&mut self, insn: u32) -> CpuAction {
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pub fn exec_arm_ldr_str_hs_imm<
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const HS: u8,
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const LOAD: bool,
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const WRITEBACK: bool,
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const PRE_INDEX: bool,
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const ADD: bool,
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>(
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&mut self,
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insn: u32,
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) -> CpuAction {
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let offset8 = (insn.bit_range(8..12) << 4) + insn.bit_range(0..4);
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let offset8 = if insn.add_offset_flag() {
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offset8
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} else {
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(-(offset8 as i32)) as u32
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};
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self.ldr_str_hs_common(insn, offset8)
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self.ldr_str_hs_common::<HS, LOAD, WRITEBACK, PRE_INDEX, ADD>(insn, offset8)
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}
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#[inline(always)]
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pub fn ldr_str_hs_common(&mut self, insn: u32, offset: u32) -> CpuAction {
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pub fn ldr_str_hs_common<
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const HS: u8,
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const LOAD: bool,
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const WRITEBACK: bool,
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const PRE_INDEX: bool,
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const ADD: bool,
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>(
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&mut self,
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insn: u32,
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offset: u32,
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) -> CpuAction {
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let mut result = CpuAction::AdvancePC(NonSeq);
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let load = insn.load_flag();
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let pre_index = insn.pre_index_flag();
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let writeback = insn.write_back_flag();
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let offset = if ADD {
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offset
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} else {
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(-(offset as i32)) as u32
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};
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let base_reg = insn.bit_range(16..20) as usize;
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let dest_reg = insn.bit_range(12..16) as usize;
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let mut addr = self.get_reg(base_reg);
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@ -412,19 +429,17 @@ impl<I: MemoryInterface> Core<I> {
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// TODO - confirm this
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let old_mode = self.cpsr.mode();
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if !pre_index && writeback {
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if !PRE_INDEX && WRITEBACK {
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self.change_mode(old_mode, CpuMode::User);
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}
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let effective_addr = (addr as i32).wrapping_add(offset as i32) as Addr;
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addr = if insn.pre_index_flag() {
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effective_addr
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} else {
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addr
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};
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addr = if PRE_INDEX { effective_addr } else { addr };
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if load {
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let data = match insn.halfword_data_transfer_type() {
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let transfer_type = ArmHalfwordTransferType::from_u8(HS).unwrap();
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if LOAD {
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let data = match transfer_type {
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ArmHalfwordTransferType::SignedByte => self.load_8(addr, NonSeq) as u8 as i8 as u32,
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ArmHalfwordTransferType::SignedHalfwords => self.ldr_sign_half(addr, NonSeq),
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ArmHalfwordTransferType::UnsignedHalfwords => self.ldr_half(addr, NonSeq),
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@ -446,7 +461,7 @@ impl<I: MemoryInterface> Core<I> {
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self.get_reg(dest_reg)
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};
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match insn.halfword_data_transfer_type() {
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match transfer_type {
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ArmHalfwordTransferType::UnsignedHalfwords => {
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self.store_aligned_16(addr, value as u16, NonSeq);
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}
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@ -454,10 +469,10 @@ impl<I: MemoryInterface> Core<I> {
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};
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}
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if !load || base_reg != dest_reg {
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if !pre_index {
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if !LOAD || base_reg != dest_reg {
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if !PRE_INDEX {
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self.set_reg(base_reg, effective_addr);
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} else if insn.write_back_flag() {
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} else if WRITEBACK {
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self.set_reg(base_reg, effective_addr);
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}
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}
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@ -367,7 +367,7 @@ impl<I: MemoryInterface> Core<I> {
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cfg_if! {
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if #[cfg(feature = "arm7tdmi_dispatch_table")] {
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fn step_arm_exec(&mut self, insn: u32) -> CpuAction {
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let hash = (((insn >> 16) & 0xff0) | ((insn >> 4) & 0x00f)) as usize;
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let hash = (((insn >> 16) & 0xff0) | ((insn >> 4) & 0xf)) as usize;
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let arm_info = &Self::ARM_LUT[hash];
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#[cfg(feature = "debugger")]
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self.debugger_record_step(DecodedInstruction::Arm(ArmInstruction::new(
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