From 44c9e2c875ce82e0638498e9dd62c6fdb847e555 Mon Sep 17 00:00:00 2001 From: Michel Heily Date: Sat, 17 Oct 2020 06:28:04 -0700 Subject: [PATCH] core: dma: Count cycles passed in DMA transfers Former-commit-id: 751f2e42f9c5c19f2fcc901754950d1e3797303b Former-commit-id: 30d31be99daec4324532d4663390945a55f641b1 --- core/src/dma.rs | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/core/src/dma.rs b/core/src/dma.rs index d8e1132..d63a228 100644 --- a/core/src/dma.rs +++ b/core/src/dma.rs @@ -1,9 +1,9 @@ +use super::arm7tdmi::memory::{MemoryAccess, MemoryInterface}; use super::cartridge::BackupMedia; use super::interrupt::{self, Interrupt, InterruptConnect, SharedInterruptFlags}; use super::iodev::consts::{REG_FIFO_A, REG_FIFO_B}; use super::sched::{EventType, Scheduler, SharedScheduler}; use super::sysbus::SysBus; -use super::Bus; use num::FromPrimitive; use serde::{Deserialize, Serialize}; @@ -151,22 +151,26 @@ impl DmaChannel { let fifo_mode = self.fifo_mode; + let mut access = MemoryAccess::NonSeq; if fifo_mode { for _ in 0..4 { - let v = sb.read_32(self.internal.src_addr & !3); - sb.write_32(self.internal.dst_addr & !3, v); + let v = sb.load_32(self.internal.src_addr & !3, access); + sb.store_32(self.internal.dst_addr & !3, v, access); + access = MemoryAccess::Seq; self.internal.src_addr += 4; } } else if word_size == 4 { for _ in 0..count { - let w = sb.read_32(self.internal.src_addr & !3); - sb.write_32(self.internal.dst_addr & !3, w); + let w = sb.load_32(self.internal.src_addr & !3, access); + sb.store_32(self.internal.dst_addr & !3, w, access); + access = MemoryAccess::Seq; self.xfer_adj_addrs(word_size); } } else { for _ in 0..count { - let hw = sb.read_16(self.internal.src_addr & !1); - sb.write_16(self.internal.dst_addr & !1, hw); + let hw = sb.load_16(self.internal.src_addr & !1, access); + sb.store_16(self.internal.dst_addr & !1, hw, access); + access = MemoryAccess::Seq; self.xfer_adj_addrs(word_size) } } @@ -240,7 +244,7 @@ impl DmaController { if self.channels[channel_id].write_dma_ctrl(value) { // DMA actually starts after 3 cycles self.scheduler - .schedule(EventType::DmaActivateChannel(channel_id), 3); + .push(EventType::DmaActivateChannel(channel_id), 3); } else { self.deactivate_channel(channel_id); }