feat(logger): Replace various println! with logs

Former-commit-id: c2f38f863d65c4564f4d2169e63714a2925a4d3f

src/core/arm7tdmi/alu.rs

@@ -73,7 +73,7 @@ impl ShiftedRegister {
     pub fn is_shifted_by_reg(&self) -> bool {
         match self.shift_by {
             ShiftRegisterBy::ByRegister(_) => true,
-            _ => false
+            _ => false,
         }
     }
 }

src/core/arm7tdmi/arm/exec.rs

@@ -363,7 +363,6 @@ impl Core {
         // TODO - confirm this
         let old_mode = self.cpsr.mode();
         if !pre_index && writeback {
-            println!("SPECIAL CHANGE MODE");
             self.change_mode(old_mode, CpuMode::User);
         }
 

src/core/arm7tdmi/exception.rs

@@ -31,7 +31,7 @@ impl Core {
             Fiq => (CpuMode::Fiq, true, true),
         };
         if self.trace_exceptions {
-            println!(
+            trace!(
                 "{}: {:?}, pc: {:#x}, new_mode: {:?} old_mode: {:?}",
                 "Exception".cyan(),
                 e,

src/core/cartridge/backup/flash.rs

@@ -163,7 +163,7 @@ impl Flash {
     }
 
     pub fn write(&mut self, addr: u32, value: u8) {
-        // println!("[FLASH] write {:#x}={:#x}", addr, value);
+        trace!("[FLASH] write {:#x}={:#x}", addr, value);
         match self.wrseq {
             FlashWriteSequence::Initial => {
                 if addr == 0x0E00_5555 && value == 0xAA {

src/core/cartridge/mod.rs

@@ -150,8 +150,8 @@ impl Cartridge {
             BackupMedia::Undetected
         };
 
-        println!("Header: {:?}", header);
+        info!("Header: {:?}", header);
-        println!("Backup: {}", backup.type_string());
+        info!("Backup: {}", backup.type_string());
 
         Cartridge {
             header: header,
@@ -193,7 +193,7 @@ fn detect_backup_type(bytes: &[u8]) -> Option<BackupType> {
             _ => {}
         }
     }
-    println!("Could not detect backup type");
+    warn!("could not detect backup type");
     return None;
 }
 

src/core/dma.rs

@@ -1,6 +1,6 @@
 use super::iodev::consts::{REG_FIFO_A, REG_FIFO_B};
 use super::sysbus::SysBus;
-use super::{Addr, Bus, Interrupt, IrqBitmask};
+use super::{Bus, Interrupt, IrqBitmask};
 
 use num::FromPrimitive;
 use serde::{Deserialize, Serialize};
@@ -86,6 +86,14 @@ impl DmaChannel {
         let timing = ctrl.timing();
         let mut start_immediately = false;
         if ctrl.is_enabled() && !self.ctrl.is_enabled() {
+            trace!(
+                "DMA{} enabled! timing={} src={:#x} dst={:#x} cnt={}",
+                self.id,
+                timing,
+                self.src,
+                self.dst,
+                self.wc
+            );
             self.start_cycles = self.cycles;
             self.running = true;
             start_immediately = timing == 0;

src/core/iodev.rs

@@ -94,11 +94,11 @@ impl Bus for IoDevices {
             REG_KEYINPUT => io.keyinput as u16,
 
             _ => {
-                // println!(
+                trace!(
-                //     "Unimplemented read from {:x} {}",
+                    "Unimplemented read from {:x} {}",
-                //     io_addr,
+                    io_addr,
-                //     io_reg_string(io_addr)
+                    io_reg_string(io_addr)
-                // );
+                );
                 0
             }
         }
@@ -244,11 +244,11 @@ impl Bus for IoDevices {
             }
 
             _ => {
-                // println!(
+                trace!(
-                //     "Unimplemented write to {:x} {}",
+                    "Unimplemented write to {:x} {}",
-                //     io_addr,
+                    io_addr,
-                //     io_reg_string(io_addr)
+                    io_reg_string(io_addr)
-                // );
+                );
             }
         }
     }

src/core/sound/mod.rs

@@ -192,12 +192,12 @@ impl SoundController {
         if io_addr == REG_SOUNDCNT_X {
             if value & bit(7) != 0 {
                 if !self.mse {
-                    println!("MSE enabled!");
+                    trace!("MSE enabled!");
                     self.mse = true;
                 }
             } else {
                 if self.mse {
-                    println!("MSE disabled!");
+                    trace!("MSE disabled!");
                     self.mse = false;
                 }
             }
@@ -207,7 +207,7 @@ impl SoundController {
         }
 
         if !self.mse {
-            // println!("MSE disabled, refusing to write");
+            warn!("MSE disabled, refusing to write");
             return;
         }
 

src/core/sysbus.rs

@@ -121,8 +121,6 @@ pub struct SysBus {
     pub trace_access: bool,
 }
 
-use ansi_term::Colour;
-
 impl SysBus {
     pub fn new(io: IoDevices, bios_rom: Vec<u8>, cartridge: Cartridge) -> SysBus {
         SysBus {
@@ -168,20 +166,10 @@ impl SysBus {
             GAMEPAK_WS0_LO | GAMEPAK_WS0_HI | GAMEPAK_WS1_LO | GAMEPAK_WS1_HI | GAMEPAK_WS2_LO => {
                 (&self.cartridge, addr)
             }
-            GAMEPAK_WS2_HI => {
+            GAMEPAK_WS2_HI => (&self.cartridge, addr),
-                // println!(
-                //     "[{}] Possible read form EEPROM",
-                //     Colour::Yellow.bold().paint("warn")
-                // );
-                (&self.cartridge, addr)
-            }
             SRAM_LO | SRAM_HI => (&self.cartridge, addr),
             _ => {
-                println!(
+                warn!("trying to read invalid address {:#x}", addr);
-                    "[{}] Trying to read address {:#x}",
-                    Colour::Yellow.bold().paint("warn"),
-                    addr
-                );
                 (&self.dummy, addr)
             }
         }
@@ -210,20 +198,10 @@ impl SysBus {
             }),
             OAM_ADDR => (&mut self.io.gpu.oam, addr & 0x3ff),
             GAMEPAK_WS0_LO | GAMEPAK_WS0_HI => (&mut self.dummy, addr),
-            GAMEPAK_WS2_HI => {
+            GAMEPAK_WS2_HI => (&mut self.cartridge, addr),
-                // println!(
-                //     "[{}] Possible write to EEPROM",
-                //     Colour::Yellow.bold().paint("warn")
-                // );
-                (&mut self.cartridge, addr)
-            }
             SRAM_LO | SRAM_HI => (&mut self.cartridge, addr),
             _ => {
-                println!(
+                warn!("trying to write invalid address {:#x}", addr);
-                    "[{}] Trying to write {:#x}",
-                    Colour::Yellow.bold().paint("warn"),
-                    addr
-                );
                 (&mut self.dummy, addr)
             }
         }
@@ -311,7 +289,7 @@ impl SysBus {
 impl Bus for SysBus {
     fn read_32(&self, addr: Addr) -> u32 {
         if addr & 3 != 0 {
-            println!("warn: Unaligned read32 at {:#X}", addr);
+            warn!("Unaligned read32 at {:#X}", addr);
         }
         let (dev, addr) = self.map(addr & !3);
         dev.read_32(addr)
@@ -319,7 +297,7 @@ impl Bus for SysBus {
 
     fn read_16(&self, addr: Addr) -> u16 {
         if addr & 1 != 0 {
-            println!("warn: Unaligned read16 at {:#X}", addr);
+            warn!("Unaligned read16 at {:#X}", addr);
         }
         let (dev, addr) = self.map(addr & !1);
         dev.read_16(addr)
@@ -332,7 +310,7 @@ impl Bus for SysBus {
 
     fn write_32(&mut self, addr: Addr, value: u32) {
         if addr & 3 != 0 {
-            println!("warn: Unaligned write32 at {:#X} (value={:#X}", addr, value);
+            warn!("Unaligned write32 at {:#X} (value={:#X}", addr, value);
         }
         let (dev, addr) = self.map_mut(addr & !3);
         dev.write_32(addr, value);
@@ -340,7 +318,7 @@ impl Bus for SysBus {
 
     fn write_16(&mut self, addr: Addr, value: u16) {
         if addr & 1 != 0 {
-            println!("warn: Unaligned write16 at {:#X} (value={:#X}", addr, value);
+            warn!("Unaligned write16 at {:#X} (value={:#X}", addr, value);
         }
         let (dev, addr) = self.map_mut(addr & !1);
         dev.write_16(addr, value);

src/core/timer.rs

@@ -104,8 +104,8 @@ impl Timers {
         } else {
             self.running_timers &= !(1 << id);
         }
-        if self.trace && old_enabled != new_enabled {
+        if old_enabled != new_enabled {
-            println!(
+            trace!(
                 "TMR{} {}",
                 id,
                 if new_enabled { "enabled" } else { "disabled" }

src/plat/sdl2/audio.rs

@@ -61,7 +61,7 @@ pub fn create_audio_player(sdl: &sdl2::Sdl) -> Sdl2AudioPlayer {
 
     let device = audio_subsystem
         .open_playback(None, &desired_spec, |spec| {
-            println!("Found audio device: {:?}", spec);
+            info!("Found audio device: {:?}", spec);
             freq = spec.freq;
 
             // Create a thread-safe SPSC fifo

src/plat/sdl2/main.rs

@@ -12,10 +12,10 @@ extern crate spin_sleep;
 use std::cell::RefCell;
 use std::rc::Rc;
 
-use std::path::{Path, PathBuf};
-use std::time;
-use std::process;
 use std::fs;
+use std::path::{Path, PathBuf};
+use std::process;
+use std::time;
 
 #[macro_use]
 extern crate clap;
@@ -60,7 +60,7 @@ fn wait_for_rom(event_pump: &mut EventPump) -> String {
 
 fn main() -> Result<(), Box<dyn std::error::Error>> {
     fs::create_dir(LOG_DIR);
-    flexi_logger::Logger::with_env()
+    flexi_logger::Logger::with_env_or_str("info")
         .log_to_file()
         .directory(LOG_DIR)
         .duplicate_to_stderr(Duplicate::Debug)