From 45f3bd6264595cc9db2fbb782f2298d8e9c7f2d0 Mon Sep 17 00:00:00 2001
From: Michel Heily <michelheily@gmail.com>
Date: Sun, 7 Jul 2019 22:57:21 +0300
Subject: [PATCH] arm: Fix STR use of R15 as the base register (Rd)

Former-commit-id: 696733731a9996ebb90b7d4acf3341facc1ed228
---
 src/arm7tdmi/arm/exec.rs | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/arm7tdmi/arm/exec.rs b/src/arm7tdmi/arm/exec.rs
index 43a683e..cc7493e 100644
--- a/src/arm7tdmi/arm/exec.rs
+++ b/src/arm7tdmi/arm/exec.rs
@@ -309,7 +309,11 @@ impl Core {
                 pipeline_action = CpuPipelineAction::Flush;
             }
         } else {
-            let value = self.get_reg(insn.rd());
+            let value = if insn.rd() == REG_PC {
+                insn.pc + 12
+            } else {
+                self.get_reg(insn.rd())
+            };
             if insn.transfer_size() == 1 {
                 self.store_8(addr, value as u8, bus);
             } else {