diff --git a/src/core/arm7tdmi/alu.rs b/src/core/arm7tdmi/alu.rs index 3607dd9..d8553c5 100644 --- a/src/core/arm7tdmi/alu.rs +++ b/src/core/arm7tdmi/alu.rs @@ -123,14 +123,11 @@ impl Core { } pub fn lsr(&mut self, val: u32, amount: u32, _carry_in: bool, immediate: bool) -> u32 { + let amount = if immediate && amount == 0 { 32 } else { amount }; match amount { - 0 | 32 => { - if immediate { - self.bs_carry_out = val.bit(31); - 0 - } else { - val - } + 32 => { + self.bs_carry_out = val.bit(31); + 0 } x if x < 32 => { self.bs_carry_out = val >> (amount - 1) & 1 == 1; @@ -143,20 +140,12 @@ impl Core { } } - pub fn asr(&mut self, val: u32, amount: u32, _carry_in: bool, immediate: bool) -> u32 { + pub fn asr(&mut self, val: u32, amount: u32, carry_in: bool, immediate: bool) -> u32 { + let amount = if immediate && amount == 0 { 32 } else { amount }; match amount { 0 => { - if immediate { - let bit31 = (val as i32 as u32).bit(31); - self.bs_carry_out = bit31; - if bit31 { - 0xffffffff - } else { - 0 - } - } else { - val - } + self.bs_carry_out = carry_in; + val } x if x < 32 => { self.bs_carry_out = val.wrapping_shr(amount - 1) & 1 == 1; diff --git a/src/core/arm7tdmi/thumb/mod.rs b/src/core/arm7tdmi/thumb/mod.rs index bd9ef72..89af391 100644 --- a/src/core/arm7tdmi/thumb/mod.rs +++ b/src/core/arm7tdmi/thumb/mod.rs @@ -282,8 +282,8 @@ impl ThumbInstruction { ThumbAluOps::from_u16(self.raw.bit_range(6..10)).unwrap() } - pub fn offset5(&self) -> i8 { - self.raw.bit_range(6..11) as i8 + pub fn offset5(&self) -> u8 { + self.raw.bit_range(6..11) as u8 } pub fn bcond_offset(&self) -> i32 {