diff --git a/src/core/arm7tdmi/arm/exec.rs b/src/core/arm7tdmi/arm/exec.rs
index bd5c427..1ef58a3 100644
--- a/src/core/arm7tdmi/arm/exec.rs
+++ b/src/core/arm7tdmi/arm/exec.rs
@@ -448,6 +448,8 @@ impl Core {
         if insn.set_cond_flag() {
             self.cpsr.set_N((result as i32) < 0);
             self.cpsr.set_Z(result == 0);
+            self.cpsr.set_C(false);
+            self.cpsr.set_V(false);
         }
 
         Ok(())
diff --git a/src/core/arm7tdmi/thumb/exec.rs b/src/core/arm7tdmi/thumb/exec.rs
index 6fd3ae3..691cb4f 100644
--- a/src/core/arm7tdmi/thumb/exec.rs
+++ b/src/core/arm7tdmi/thumb/exec.rs
@@ -85,7 +85,10 @@ impl Core {
         for _ in 0..m {
             self.add_cycle();
         }
-        self.gpr[insn.rd()] = op1.wrapping_mul(op2) as u32;
+        let result = op1.wrapping_mul(op2) as u32;
+        self.cpsr.set_N((result as i32) < 0);
+        self.cpsr.set_Z(result == 0);
+        self.gpr[insn.rd()] = result;
         Ok(())
     }