diff --git a/rustboyadvance-core/src/arm7tdmi/alu.rs b/rustboyadvance-core/src/arm7tdmi/alu.rs
index e31414f..d114326 100644
--- a/rustboyadvance-core/src/arm7tdmi/alu.rs
+++ b/rustboyadvance-core/src/arm7tdmi/alu.rs
@@ -223,6 +223,9 @@ impl Core {
         carry_in: bool,
         immediate: bool,
     ) -> u32 {
+        // TODO get rid of Core::bs_carry_out field in favour sending the carry as a &mut reference,
+        // Forcing calling functions to do something with the carry :
+        self.bs_carry_out = carry_in;
         //
         // From GBATEK:
         // Zero Shift Amount (Shift Register by Immediate, with Immediate=0)
diff --git a/rustboyadvance-core/src/arm7tdmi/arm/exec.rs b/rustboyadvance-core/src/arm7tdmi/arm/exec.rs
index cff3beb..50fb107 100644
--- a/rustboyadvance-core/src/arm7tdmi/arm/exec.rs
+++ b/rustboyadvance-core/src/arm7tdmi/arm/exec.rs
@@ -193,19 +193,20 @@ impl Core {
 
         let rn = raw_insn.bit_range(16..20) as usize;
         let rd = raw_insn.bit_range(12..16) as usize;
-
         let mut op1 = if rn == REG_PC {
             insn.pc + 8
         } else {
             self.get_reg(rn)
         };
-
         let mut s_flag = insn.set_cond_flag();
         let opcode = insn.opcode();
 
         let op2 = if raw_insn.bit(25) {
             let immediate = raw_insn & 0xff;
             let rotate = 2 * raw_insn.bit_range(8..12);
+            // TODO refactor out
+            let bs_carry_in = self.cpsr.C();
+            self.bs_carry_out = bs_carry_in;
             self.ror(immediate, rotate, self.cpsr.C(), false, true)
         } else {
             let reg = raw_insn & 0xf;