arm: Implement MRS
Former-commit-id: 8c1528b2bcd08096f929c4ee940f1a1f5eac2911
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5f625b2209
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@ -5,7 +5,7 @@ use crate::arm7tdmi::bus::Bus;
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use crate::arm7tdmi::cpu::{Core, CpuExecResult, CpuPipelineAction};
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use crate::arm7tdmi::exception::Exception;
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use crate::arm7tdmi::psr::RegPSR;
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use crate::arm7tdmi::{Addr, CpuError, CpuResult, CpuState, DecodedInstruction, REG_PC};
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use crate::arm7tdmi::{Addr, CpuError, CpuMode, CpuResult, CpuState, DecodedInstruction, REG_PC};
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use super::*;
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@ -23,6 +23,7 @@ impl Core {
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ArmFormat::LDR_STR_HS_IMM => self.exec_ldr_str_hs(bus, insn),
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ArmFormat::LDR_STR_HS_REG => self.exec_ldr_str_hs(bus, insn),
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ArmFormat::LDM_STM => self.exec_ldm_stm(bus, insn),
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ArmFormat::MRS => self.exec_mrs(bus, insn),
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ArmFormat::MSR_REG => self.exec_msr_reg(bus, insn),
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ArmFormat::MSR_FLAGS => self.exec_msr_flags(bus, insn),
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ArmFormat::MUL_MLA => self.exec_mul_mla(bus, insn),
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@ -69,6 +70,21 @@ impl Core {
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Ok(CpuPipelineAction::Flush)
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}
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fn exec_mrs(&mut self, _bus: &mut Bus, insn: ArmInstruction) -> CpuExecResult {
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let mode = self.cpsr.mode();
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let result = if insn.spsr_flag() {
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if let Some(index) = mode.spsr_index() {
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self.spsr[index].get()
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} else {
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panic!("tried to get spsr from invalid mode {}", mode)
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}
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} else {
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self.cpsr.get()
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};
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self.set_reg(insn.rd(), result);
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Ok(CpuPipelineAction::IncPC)
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}
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fn exec_msr_reg(&mut self, _bus: &mut Bus, insn: ArmInstruction) -> CpuExecResult {
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self.exec_msr(insn, self.get_reg(insn.rm()))
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}
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