Impl Thumb 18 (Branch)
Former-commit-id: 152dab739a1fa1b9d324084fc810b8540af9c3d7
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@ -170,6 +170,17 @@ impl ThumbInstruction {
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)
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}
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fn fmt_thumb_branch(&self, f: &mut fmt::Formatter) -> fmt::Result {
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write!(
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f,
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"b\t{addr:#x}",
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addr = {
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let offset = (self.offset11() << 21) >> 20;
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(self.pc as i32 + 4).wrapping_add(offset) as Addr
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}
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)
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}
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fn fmt_thumb_branch_long_with_link(&self, f: &mut fmt::Formatter) -> fmt::Result {
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write!(f, "bl\t#0x{:08x}", {
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let offset11 = self.offset11();
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@ -198,6 +209,7 @@ impl fmt::Display for ThumbInstruction {
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ThumbFormat::AddSp => self.fmt_thumb_add_sp(f),
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ThumbFormat::PushPop => self.fmt_thumb_push_pop(f),
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ThumbFormat::BranchConditional => self.fmt_thumb_branch_with_cond(f),
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ThumbFormat::Branch => self.fmt_thumb_branch(f),
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ThumbFormat::BranchLongWithLink => self.fmt_thumb_branch_long_with_link(f),
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_ => write!(f, "({:?})", self),
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}
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@ -132,11 +132,11 @@ impl Core {
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insn.rs()
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};
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let arm_alu_op: ArmOpCode = insn.format5_op().into();
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let op1 = self.gpr[dst_reg] as i32;
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let op2 = self.gpr[src_reg] as i32;
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let op1 = self.get_reg(dst_reg) as i32;
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let op2 = self.get_reg(src_reg) as i32;
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let result = self.alu(arm_alu_op, op1, op2, true);
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if let Some(result) = result {
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self.gpr[dst_reg] = result as u32;
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self.set_reg(dst_reg, result as u32);
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}
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Ok(CpuPipelineAction::IncPC)
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}
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@ -269,6 +269,16 @@ impl Core {
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}
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}
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fn exec_thumb_branch(
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&mut self,
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_bus: &mut Bus,
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insn: ThumbInstruction,
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) -> CpuExecResult {
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let offset = ((insn.offset11() << 21) >> 20) as i32;
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self.pc = (self.pc as i32).wrapping_add(offset) as u32;
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Ok(CpuPipelineAction::Flush)
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}
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fn exec_thumb_branch_long_with_link(
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&mut self,
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_bus: &mut Bus,
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@ -305,6 +315,7 @@ impl Core {
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ThumbFormat::AddSp => self.exec_thumb_add_sp(bus, insn),
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ThumbFormat::PushPop => self.exec_thumb_push_pop(bus, insn),
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ThumbFormat::BranchConditional => self.exec_thumb_branch_with_cond(bus, insn),
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ThumbFormat::Branch => self.exec_thumb_branch(bus, insn),
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ThumbFormat::BranchLongWithLink => self.exec_thumb_branch_long_with_link(bus, insn),
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_ => unimplemented!("thumb not implemented {:#x?}", insn),
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}
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