cpu: Kinda implement data processing instructions
When I say "Kinda", I mean that it is not tested well.
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5808c03fcd
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6552329310
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@ -1,6 +1,6 @@
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use super::super::{reg_string, REG_PC};
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use super::{
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ArmCond, ArmHalfwordTransferType, ArmInstruction, ArmInstructionFormat, ArmOpCode, ArmShift,
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ArmCond, ArmHalfwordTransferType, ArmInstruction, ArmInstructionFormat, ArmOpCode, ArmRegisterShift,
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ArmShiftType, ArmShiftedValue,
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};
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use std::fmt;
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@ -75,23 +75,23 @@ impl fmt::Display for ArmHalfwordTransferType {
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}
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}
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fn is_shift(shift: &ArmShift) -> bool {
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if let ArmShift::ImmediateShift(val, typ) = shift {
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fn is_shift(shift: &ArmRegisterShift) -> bool {
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if let ArmRegisterShift::ShiftAmount(val, typ) = shift {
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return !(*val == 0 && *typ == ArmShiftType::LSL);
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}
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true
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}
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impl ArmInstruction {
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fn make_shifted_reg_string(&self, reg: usize, shift: ArmShift) -> String {
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fn make_shifted_reg_string(&self, reg: usize, shift: ArmRegisterShift) -> String {
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let reg = reg_string(reg).to_string();
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if !is_shift(&shift) {
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return reg;
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}
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match shift {
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ArmShift::ImmediateShift(imm, typ) => format!("{}, {} #{}", reg, typ, imm),
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ArmShift::RegisterShift(rs, typ) => format!("{}, {} {}", reg, typ, reg_string(rs)),
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ArmRegisterShift::ShiftAmount(imm, typ) => format!("{}, {} #{}", reg, typ, imm),
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ArmRegisterShift::ShiftRegister(rs, typ) => format!("{}, {} {}", reg, typ, reg_string(rs)),
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}
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}
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@ -1,11 +1,61 @@
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use super::super::cpu::{Core, CpuState, CpuPipelineAction, CpuError, CpuInstruction, CpuResult, CpuExecResult};
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use super::super::cpu::{
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Core, CpuError, CpuExecResult, CpuInstruction, CpuPipelineAction, CpuResult,
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};
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use super::super::psr::CpuState;
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use super::super::sysbus::SysBus;
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use super::{ArmInstruction, ArmInstructionFormat};
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use super::{
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ArmCond, ArmInstruction, ArmInstructionFormat, ArmOpCode, ArmRegisterShift, ArmShiftType,
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ArmShiftedValue,
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};
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use crate::bit::BitIndex;
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impl Core {
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fn exec_b_bl(&mut self, sysbus: &mut SysBus, insn: ArmInstruction) -> CpuResult<CpuPipelineAction> {
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fn check_arm_cond(&self, cond: ArmCond) -> bool {
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use ArmCond::*;
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match cond {
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Equal => self.cpsr.Z(),
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NotEqual => !self.cpsr.Z(),
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UnsignedHigherOrSame => self.cpsr.C(),
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UnsignedLower => !self.cpsr.C(),
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Negative => self.cpsr.N(),
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PositiveOrZero => !self.cpsr.N(),
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Overflow => self.cpsr.V(),
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NoOverflow => !self.cpsr.V(),
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UnsignedHigher => self.cpsr.C() && !self.cpsr.Z(),
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UnsignedLowerOrSame => !self.cpsr.C() && self.cpsr.Z(),
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GreaterOrEqual => self.cpsr.N() == self.cpsr.V(),
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LessThan => self.cpsr.N() != self.cpsr.V(),
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GreaterThan => !self.cpsr.Z() && (self.cpsr.N() == self.cpsr.V()),
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LessThanOrEqual => self.cpsr.Z() || (self.cpsr.N() != self.cpsr.V()),
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Always => true,
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}
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}
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pub fn exec_arm(&mut self, sysbus: &mut SysBus, insn: ArmInstruction) -> CpuExecResult {
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let action = if self.check_arm_cond(insn.cond) {
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match insn.fmt {
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ArmInstructionFormat::BX => self.exec_bx(sysbus, insn),
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ArmInstructionFormat::B_BL => self.exec_b_bl(sysbus, insn),
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ArmInstructionFormat::DP => self.exec_data_processing(sysbus, insn),
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_ => Err(CpuError::UnimplementedCpuInstruction(CpuInstruction::Arm(
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insn,
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))),
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}
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} else {
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Ok(CpuPipelineAction::AdvanceProgramCounter)
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}?;
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Ok((CpuInstruction::Arm(insn), action))
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}
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fn exec_b_bl(
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&mut self,
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_sysbus: &mut SysBus,
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insn: ArmInstruction,
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) -> CpuResult<CpuPipelineAction> {
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if self.verbose && insn.cond != ArmCond::Always {
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println!("branch taken!")
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}
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if insn.link_flag() {
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self.set_reg(14, self.pc & !0b1);
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}
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@ -13,23 +63,113 @@ impl Core {
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Ok(CpuPipelineAction::Branch)
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}
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fn exec_bx(&mut self, sysbus: &mut SysBus, insn: ArmInstruction) -> CpuResult<CpuPipelineAction> {
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fn exec_bx(
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&mut self,
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_sysbus: &mut SysBus,
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insn: ArmInstruction,
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) -> CpuResult<CpuPipelineAction> {
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let rn = self.get_reg(insn.rn());
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if rn.bit(0) {
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self.set_state(CpuState::THUMB);
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self.cpsr.set_state(CpuState::THUMB);
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} else {
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self.set_state(CpuState::ARM);
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self.cpsr.set_state(CpuState::ARM);
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}
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Ok(CpuPipelineAction::Branch)
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}
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pub fn exec_arm(&mut self, sysbus: &mut SysBus, insn: ArmInstruction) -> CpuExecResult {
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let action = match insn.fmt {
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ArmInstructionFormat::BX => self.exec_bx(sysbus, insn),
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ArmInstructionFormat::B_BL => self.exec_b_bl(sysbus, insn),
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fmt => Err(CpuError::UnimplementedCpuInstruction(CpuInstruction::Arm(insn))),
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}?;
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Ok((CpuInstruction::Arm(insn), action))
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fn do_shift(val: i32, amount: u32, shift: ArmShiftType) -> i32 {
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match shift {
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ArmShiftType::LSL => val.wrapping_shl(amount),
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ArmShiftType::LSR => (val as u32).wrapping_shr(amount) as i32,
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ArmShiftType::ASR => val.wrapping_shr(amount),
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ArmShiftType::ROR => val.rotate_right(amount),
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}
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}
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}
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fn register_shift(&mut self, reg: usize, shift: ArmRegisterShift) -> i32 {
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let val = self.get_reg(reg) as i32;
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match shift {
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ArmRegisterShift::ShiftAmount(amount, shift) => Core::do_shift(val, amount, shift),
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ArmRegisterShift::ShiftRegister(reg, shift) => {
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Core::do_shift(val, self.get_reg(reg) & 0xff, shift)
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}
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}
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}
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fn alu_sub_update_carry(a: i32, b: i32, carry: &mut bool) -> i32 {
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let res = a.wrapping_sub(b);
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*carry = res > a;
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res
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}
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fn alu_add_update_carry(a: i32, b: i32, carry: &mut bool) -> i32 {
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let res = a.wrapping_sub(b);
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*carry = res < a;
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res
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}
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fn alu(&mut self, opcode: ArmOpCode, op1: i32, op2: i32, set_cond_flags: bool) -> Option<i32> {
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let C = self.cpsr.C() as i32;
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let mut carry = self.cpsr.C();
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let mut overflow = self.cpsr.V();
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let result = match opcode {
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ArmOpCode::AND | ArmOpCode::TST => op1 & op2,
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ArmOpCode::EOR | ArmOpCode::TEQ => op1 ^ op2,
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ArmOpCode::SUB | ArmOpCode::CMP => Self::alu_sub_update_carry(op1, op2, &mut carry),
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ArmOpCode::RSB => Self::alu_sub_update_carry(op2, op1, &mut carry),
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ArmOpCode::ADD | ArmOpCode::CMN => Self::alu_add_update_carry(op1, op2, &mut carry),
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ArmOpCode::ADC => Self::alu_add_update_carry(op1, op2.wrapping_add(C), &mut carry),
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ArmOpCode::SBC => Self::alu_add_update_carry(op1, op2.wrapping_sub(1 - C), &mut carry),
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ArmOpCode::RSC => Self::alu_add_update_carry(op2, op1.wrapping_sub(1 - C), &mut carry),
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ArmOpCode::ORR => op1 | op2,
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ArmOpCode::MOV => op2,
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ArmOpCode::BIC => op1 & (!op2),
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ArmOpCode::MVN => !op2,
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};
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if set_cond_flags {
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self.cpsr.set_N(result < 0);
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self.cpsr.set_Z(result == 0);
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self.cpsr.set_C(carry);
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self.cpsr.set_V(overflow);
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}
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match opcode {
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ArmOpCode::TST | ArmOpCode::TEQ | ArmOpCode::CMP | ArmOpCode::CMN => None,
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_ => Some(result),
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}
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}
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fn exec_data_processing(
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&mut self,
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_sysbus: &mut SysBus,
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insn: ArmInstruction,
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) -> CpuResult<CpuPipelineAction> {
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// TODO handle carry flag
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let op1 = self.get_reg(insn.rn()) as i32;
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let op2 = insn.operand2()?;
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let op2: i32 = match op2 {
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ArmShiftedValue::RotatedImmediate(immediate, rotate) => {
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immediate.rotate_right(rotate) as i32
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}
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ArmShiftedValue::ShiftedRegister {
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reg,
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shift,
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added: _,
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} => self.register_shift(reg, shift),
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_ => unreachable!(),
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};
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let opcode = insn.opcode().unwrap();
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if let Some(result) = self.alu(opcode, op1, op2, insn.set_cond_flag()) {
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self.set_reg(insn.rd(), result as u32)
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}
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Ok(CpuPipelineAction::AdvanceProgramCounter)
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}
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}
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@ -184,12 +184,12 @@ pub enum ArmShiftType {
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}
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#[derive(Debug, PartialEq)]
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pub enum ArmShift {
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ImmediateShift(u32, ArmShiftType),
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RegisterShift(usize, ArmShiftType),
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pub enum ArmRegisterShift {
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ShiftAmount(u32, ArmShiftType),
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ShiftRegister(usize, ArmShiftType),
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}
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impl TryFrom<u32> for ArmShift {
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impl TryFrom<u32> for ArmRegisterShift {
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type Error = ArmDecodeErrorKind;
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fn try_from(v: u32) -> Result<Self, Self::Error> {
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@ -199,10 +199,10 @@ impl TryFrom<u32> for ArmShift {
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}?;
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if v.bit(4) {
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let rs = v.bit_range(8..12) as usize;
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Ok(ArmShift::RegisterShift(rs, typ))
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Ok(ArmRegisterShift::ShiftRegister(rs, typ))
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} else {
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let amount = v.bit_range(7..12) as u32;
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Ok(ArmShift::ImmediateShift(amount, typ))
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Ok(ArmRegisterShift::ShiftAmount(amount, typ))
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}
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}
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}
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@ -213,7 +213,7 @@ pub enum ArmShiftedValue {
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RotatedImmediate(u32, u32),
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ShiftedRegister {
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reg: usize,
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shift: ArmShift,
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shift: ArmRegisterShift,
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added: Option<bool>,
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},
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}
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@ -338,7 +338,7 @@ impl ArmInstruction {
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let ofs = self.raw.bit_range(0..12);
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if self.raw.bit(25) {
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let rm = ofs & 0xf;
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let shift = ArmShift::try_from(ofs).map_err(|kind| self.make_decode_error(kind))?;
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let shift = ArmRegisterShift::try_from(ofs).map_err(|kind| self.make_decode_error(kind))?;
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Ok(ArmShiftedValue::ShiftedRegister {
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reg: rm as usize,
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shift: shift,
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@ -367,7 +367,7 @@ impl ArmInstruction {
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}
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ArmInstructionFormat::LDR_STR_HS_REG => Ok(ArmShiftedValue::ShiftedRegister {
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reg: (self.raw & 0xf) as usize,
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shift: ArmShift::ImmediateShift(0, ArmShiftType::LSL),
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shift: ArmRegisterShift::ShiftAmount(0, ArmShiftType::LSL),
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added: Some(self.add_offset_flag()),
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}),
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_ => Err(self.make_decode_error(DecodedPartDoesNotBelongToInstruction)),
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@ -382,7 +382,7 @@ impl ArmInstruction {
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Ok(ArmShiftedValue::RotatedImmediate(immediate, rotate))
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} else {
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let reg = op2 & 0xf;
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let shift = ArmShift::try_from(op2).map_err(|kind| self.make_decode_error(kind))?; // TODO error handling
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let shift = ArmRegisterShift::try_from(op2).map_err(|kind| self.make_decode_error(kind))?; // TODO error handling
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Ok(ArmShiftedValue::ShiftedRegister {
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reg: reg as usize,
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shift: shift,
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@ -69,7 +69,7 @@ pub struct Core {
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#[derive(Debug, PartialEq)]
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pub enum CpuPipelineAction {
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AdvancePc,
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AdvanceProgramCounter,
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Branch,
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}
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@ -145,7 +145,7 @@ impl Core {
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}
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}
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if CpuPipelineAction::AdvancePc == pipeline_action {
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if CpuPipelineAction::AdvanceProgramCounter == pipeline_action {
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self.advance_pc();
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}
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@ -1,3 +1,4 @@
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mod psr;
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pub mod arm;
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pub mod cpu;
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pub use super::sysbus;
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@ -91,7 +91,7 @@ fn run_debug(matches: &ArgMatches) -> GBAResult<()> {
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println!("Loading BIOS: {}", gba_bios_path);
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let bios_bin = read_bin_file(gba_bios_path)?;
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let mut sysbus = SysBus::new(bios_bin);
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let sysbus = SysBus::new(bios_bin);
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let mut core = cpu::Core::new();
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core.set_verbose(true);
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let mut debugger = Debugger::new(core, sysbus);
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