Implement all memory mappings. Reformat many files.
Former-commit-id: c0a62b610e62d2db2a4daf4aeef40068820daa52
This commit is contained in:
Michel Heily
parent
22c175d9cc
commit
6b225d776d
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@ -1,10 +1,10 @@
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use std::fmt;
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use crate::arm7tdmi::{Addr, reg_string, REG_PC};
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use super::{
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ArmCond, ArmHalfwordTransferType, ArmInstruction, ArmInstructionFormat, ArmOpCode,
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ArmRegisterShift, ArmShiftType, ArmShiftedValue,
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};
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use crate::arm7tdmi::{reg_string, Addr, REG_PC};
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impl fmt::Display for ArmCond {
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fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
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@ -1,8 +1,8 @@
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use crate::bit::BitIndex;
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use crate::arm7tdmi::bus::{Bus, MemoryAccess, MemoryAccessType::*, MemoryAccessWidth::*};
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use crate::arm7tdmi::cpu::{Core, CpuExecResult, CpuPipelineAction};
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use crate::arm7tdmi::exception::Exception;
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use crate::arm7tdmi::bus::{Bus, MemoryAccess, MemoryAccessType::*, MemoryAccessWidth::*};
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use crate::arm7tdmi::{Addr, CpuError, CpuInstruction, CpuResult, CpuState, REG_PC};
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use crate::sysbus::SysBus;
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@ -15,7 +15,11 @@ use super::{
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impl Core {
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pub fn exec_arm(&mut self, sysbus: &mut SysBus, insn: ArmInstruction) -> CpuExecResult {
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if !self.check_arm_cond(insn.cond) {
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self.add_cycles(self.pc + (self.word_size() as u32), sysbus, Seq + MemoryAccess32);
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self.add_cycles(
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insn.pc + (self.word_size() as u32),
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sysbus,
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Seq + MemoryAccess32,
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);
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self.add_cycle();
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return Ok(CpuPipelineAction::IncPC);
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}
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@ -40,7 +44,7 @@ impl Core {
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if insn.link_flag() {
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self.set_reg(14, self.pc & !0b1);
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}
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// +1N
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self.add_cycles(self.pc, sysbus, NonSeq + MemoryAccess32);
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@ -48,7 +52,11 @@ impl Core {
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// +2S
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self.add_cycles(self.pc, sysbus, Seq + MemoryAccess32);
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self.add_cycles(self.pc + (self.word_size() as u32), sysbus, Seq + MemoryAccess32);
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self.add_cycles(
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self.pc + (self.word_size() as u32),
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sysbus,
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Seq + MemoryAccess32,
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);
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Ok(CpuPipelineAction::Flush)
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}
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@ -68,12 +76,16 @@ impl Core {
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// +1N
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self.add_cycles(self.pc, sysbus, NonSeq + MemoryAccess32);
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self.pc = rn & !1;
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// +2S
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self.add_cycles(self.pc, sysbus, Seq + MemoryAccess32);
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self.add_cycles(self.pc + (self.word_size() as u32), sysbus, Seq + MemoryAccess32);
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self.add_cycles(
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self.pc + (self.word_size() as u32),
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sysbus,
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Seq + MemoryAccess32,
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);
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Ok(CpuPipelineAction::Flush)
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}
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@ -159,7 +171,7 @@ impl Core {
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}
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/// Logical/Arithmetic ALU operations
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///
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///
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/// Cycles: 1S+x+y (from GBATEK)
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/// Add x=1I cycles if Op2 shifted-by-register. Add y=1S+1N cycles if Rd=R15.
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fn exec_data_processing(
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@ -208,7 +220,11 @@ impl Core {
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}
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// +1S
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self.add_cycles(self.pc + (self.word_size() as u32), sysbus, Seq + MemoryAccess32);
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self.add_cycles(
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self.pc + (self.word_size() as u32),
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sysbus,
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Seq + MemoryAccess32,
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);
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Ok(pipeline_action)
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}
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@ -219,12 +235,16 @@ impl Core {
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ArmShiftedValue::ShiftedRegister {
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reg,
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shift,
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added: Some(added)
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added: Some(added),
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} => {
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let abs = self.register_shift(reg, shift).unwrap();
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if added { abs } else { -abs }
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if added {
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abs
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} else {
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-abs
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}
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}
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_ => panic!("bad barrel shift")
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_ => panic!("bad barrel shift"),
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}
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}
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@ -240,7 +260,6 @@ impl Core {
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sysbus: &mut SysBus,
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insn: ArmInstruction,
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) -> CpuResult<CpuPipelineAction> {
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if insn.write_back_flag() && insn.rd() == insn.rn() {
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return Err(CpuError::IllegalInstruction);
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}
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@ -258,7 +277,7 @@ impl Core {
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let effective_addr = (addr as i32).wrapping_add(offset) as Addr;
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addr = if insn.pre_index_flag() {
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effective_addr
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} else {
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} else {
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addr
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};
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@ -273,8 +292,12 @@ impl Core {
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sysbus.read_32(addr)
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};
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// +1S
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self.add_cycles(self.pc + (self.word_size() as u32), sysbus, Seq + MemoryAccess32);
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self.add_cycles(
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self.pc + (self.word_size() as u32),
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sysbus,
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Seq + MemoryAccess32,
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);
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self.set_reg(insn.rd(), data);
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// +1I
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@ -284,7 +307,11 @@ impl Core {
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// +1S
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self.add_cycles(self.pc, sysbus, Seq + MemoryAccess32);
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// +1N
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self.add_cycles(self.pc + (self.word_size() as u32), sysbus, NonSeq + MemoryAccess32);
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self.add_cycles(
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self.pc + (self.word_size() as u32),
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sysbus,
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NonSeq + MemoryAccess32,
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);
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pipeline_action = CpuPipelineAction::Flush;
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}
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} else {
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@ -293,11 +320,11 @@ impl Core {
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if insn.transfer_size() == 1 {
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// +1N
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self.add_cycles(dest, sysbus, NonSeq + MemoryAccess8);
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sysbus.write_8(addr, value as u8);
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sysbus.write_8(addr, value as u8).expect("bus error");
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} else {
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// +1N
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self.add_cycles(dest, sysbus, NonSeq + MemoryAccess32);
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sysbus.write_32(addr, value);
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sysbus.write_32(addr, value).expect("bus error");
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};
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}
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@ -305,6 +332,6 @@ impl Core {
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self.set_reg(insn.rn(), effective_addr as u32)
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}
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Ok(CpuPipelineAction::IncPC)
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Ok(pipeline_action)
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}
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}
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@ -1,19 +1,20 @@
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use super::Addr;
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use std::io;
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use std::ops::Add;
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use super::Addr;
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use byteorder::{LittleEndian, ReadBytesExt, WriteBytesExt};
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pub enum MemoryAccessType {
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NonSeq,
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Seq
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Seq,
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}
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pub enum MemoryAccessWidth {
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MemoryAccess8,
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MemoryAccess16,
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MemoryAccess32
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MemoryAccess32,
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}
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impl Add<MemoryAccessWidth> for MemoryAccessType {
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type Output = MemoryAccess;
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@ -22,17 +23,40 @@ impl Add<MemoryAccessWidth> for MemoryAccessType {
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}
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}
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pub struct MemoryAccess(MemoryAccessType, MemoryAccessWidth);
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pub struct MemoryAccess(pub MemoryAccessType, pub MemoryAccessWidth);
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pub trait Bus {
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fn read_32(&self, addr: Addr) -> u32;
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fn read_16(&self, addr: Addr) -> u16;
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fn read_8(&self, addr: Addr) -> u8;
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fn write_32(&mut self, addr: Addr, value: u32) -> Result<(), io::Error>;
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fn write_16(&mut self, addr: Addr, value: u16) -> Result<(), io::Error>;
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fn write_8(&mut self, addr: Addr, value: u8) -> Result<(), io::Error>;
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fn read_32(&self, addr: Addr) -> u32 {
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self.get_bytes(addr, 4).read_u32::<LittleEndian>().unwrap()
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}
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fn read_16(&self, addr: Addr) -> u16 {
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self.get_bytes(addr, 2).read_u16::<LittleEndian>().unwrap()
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}
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fn read_8(&self, addr: Addr) -> u8 {
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self.get_bytes(addr, 1)[0]
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}
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fn write_32(&mut self, addr: Addr, value: u32) -> Result<(), io::Error> {
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self.get_bytes_mut(addr, 4).write_u32::<LittleEndian>(value)
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}
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fn write_16(&mut self, addr: Addr, value: u16) -> Result<(), io::Error> {
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self.get_bytes_mut(addr, 2).write_u16::<LittleEndian>(value)
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}
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fn write_8(&mut self, addr: Addr, value: u8) -> Result<(), io::Error> {
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self.get_bytes_mut(addr, 1).write_u8(value)
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}
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/// Return a slice of bytes
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/// Will panic if requested range is out of bounds
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fn get_bytes(&self, addr: Addr, len: usize) -> &[u8];
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/// Return a mutable slice of bytes
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/// Will panic if requested range is out of bounds
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fn get_bytes_mut(&mut self, addr: Addr, len: usize) -> &mut [u8];
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fn get_bytes(&self, addr: Addr, size: usize) -> Option<&[u8]>;
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/// returns the number of cycles needed for this memory access
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fn get_cycles(&self, addr: Addr, access: MemoryAccess) -> usize;
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}
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}
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@ -1,6 +1,6 @@
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use std::ops::Add;
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use std::convert::TryFrom;
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use std::fmt;
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use std::ops::Add;
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use ansi_term::{Colour, Style};
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@ -8,10 +8,10 @@ use crate::sysbus::SysBus;
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pub use super::exception::Exception;
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use super::{
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CpuState, CpuMode, reg_string, CpuResult, Addr,
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psr::RegPSR,
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arm::*,
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bus::{Bus, MemoryAccess, MemoryAccessType::*, MemoryAccessWidth::*},
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arm::*
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psr::RegPSR,
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reg_string, Addr, CpuMode, CpuResult, CpuState,
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};
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#[derive(Debug, Default)]
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@ -198,9 +198,7 @@ impl Core {
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let action = self.exec_arm(sysbus, d)?;
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Ok((Some(d), action))
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}
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None => {
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Ok((None, CpuPipelineAction::IncPC))
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},
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None => Ok((None, CpuPipelineAction::IncPC)),
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};
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self.pipeline.fetched = Some((self.pc, new_fetched));
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@ -1,14 +1,14 @@
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use std::fmt;
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pub mod arm;
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use arm::{ArmInstruction, ArmDecodeError};
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use arm::{ArmDecodeError, ArmInstruction};
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pub mod cpu;
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pub use cpu::*;
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pub mod bus;
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mod exception;
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mod psr;
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pub const REG_PC: usize = 15;
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pub const REG_LR: usize = 14;
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pub const REG_SP: usize = 13;
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@ -5,11 +5,17 @@ subcommands:
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- debug:
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about: debug the bios with the arm core emulation
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args:
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- BIOS:
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- bios:
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help: Sets the bios file to use
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required: false
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default_value: gba_bios.bin
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index: 1
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- game_rom:
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short: g
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long: game-rom
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takes_value: true
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help: Sets the game-rom file to use
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required: true
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- disass:
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about: disassemble an arm binary file
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args:
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@ -8,9 +8,9 @@ use clap::{App, ArgMatches};
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extern crate rustboyadvance_ng;
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use rustboyadvance_ng::arm7tdmi;
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use rustboyadvance_ng::sysbus::SysBus;
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use rustboyadvance_ng::debugger::{Debugger, DebuggerError};
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use rustboyadvance_ng::disass::Disassembler;
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use rustboyadvance_ng::sysbus::SysBus;
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use rustboyadvance_ng::util::read_bin_file;
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#[derive(Debug)]
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@ -18,7 +18,7 @@ pub enum GBAError {
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IO(io::Error),
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ArmDecodeError(arm7tdmi::arm::ArmDecodeError),
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CpuError(arm7tdmi::CpuError),
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DebuggerError(DebuggerError)
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DebuggerError(DebuggerError),
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}
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pub type GBAResult<T> = Result<T, GBAError>;
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@ -59,11 +59,10 @@ fn run_disass(matches: &ArgMatches) -> GBAResult<()> {
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}
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fn run_debug(matches: &ArgMatches) -> GBAResult<()> {
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let gba_bios_path = matches.value_of("BIOS").unwrap_or_default();
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println!("Loading BIOS: {}", gba_bios_path);
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let bios_bin = read_bin_file(gba_bios_path)?;
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let bios_bin = read_bin_file(matches.value_of("bios").unwrap_or_default())?;
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let rom_bin = read_bin_file(matches.value_of("game_rom").unwrap())?;
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let sysbus = SysBus::new(bios_bin);
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let sysbus = SysBus::new(bios_bin, rom_bin);
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let mut core = arm7tdmi::cpu::Core::new();
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core.reset();
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core.set_verbose(true);
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@ -1,5 +1,5 @@
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use crate::arm7tdmi::{reg_string, REG_PC};
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use crate::arm7tdmi::bus::Bus;
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use crate::arm7tdmi::{reg_string, REG_PC};
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use crate::debugger::Debugger;
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use crate::disass::Disassembler;
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@ -59,11 +59,11 @@ impl Command {
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match debugger.cpu.step_debugger(&mut debugger.sysbus) {
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Ok(insn) => {
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println!(
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"@0x{:08x}:\n\t{}",
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insn.pc,
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Colour::Yellow.italic().paint(format!("{} ", insn))
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);
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},
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"@0x{:08x}:\n\t{}",
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insn.pc,
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Colour::Yellow.italic().paint(format!("{} ", insn))
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);
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}
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Err(e) => {
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println!("{}: {}", "cpu encountered an error".red(), e);
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println!("cpu: {:x?}", debugger.cpu);
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@ -72,23 +72,11 @@ impl Command {
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};
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},
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HexDump(addr, nbytes) => {
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let bytes = match debugger.sysbus.get_bytes(addr, nbytes) {
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Some(bytes) => bytes,
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None => {
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println!("requested content out of bounds");
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return;
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}
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};
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let bytes = debugger.sysbus.get_bytes(addr, nbytes);
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hexdump::hexdump(bytes);
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}
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Disass(addr, n) => {
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let bytes = match debugger.sysbus.get_bytes(addr, 4 * n) {
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Some(bytes) => bytes,
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None => {
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println!("requested content out of bounds");
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return;
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}
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};
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let bytes = debugger.sysbus.get_bytes(addr, 4 * n);
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let disass = Disassembler::new(addr, bytes);
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for (_, line) in disass {
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println!("{}", line)
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|
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@ -171,7 +171,7 @@ impl Debugger {
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if let Some(Command::Disass(addr, n)) = self.previous_command {
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(addr + (4 * n as u32), 10)
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} else {
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(self.cpu.get_reg(15), 10)
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(self.cpu.get_next_pc(), 10)
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}
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}
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_ => {
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|
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181
src/sysbus.rs
181
src/sysbus.rs
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@ -1,132 +1,163 @@
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use std::io;
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use super::arm7tdmi::bus::{Bus, MemoryAccess, MemoryAccessWidth};
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use super::arm7tdmi::Addr;
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use super::arm7tdmi::bus::{Bus, MemoryAccess, MemoryAccessType, MemoryAccessWidth};
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use byteorder::{LittleEndian, ReadBytesExt, WriteBytesExt};
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const VIDEO_RAM_SIZE: usize = 128 * 1024;
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const WORK_RAM_SIZE: usize = 256 * 1024;
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const INTERNAL_RAM: usize = 32 * 1024;
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const PALETTE_AM_SIZE: usize = 1 * 1024;
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const PALETTE_RAM_SIZE: usize = 1 * 1024;
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const OAM_SIZE: usize = 1 * 1024;
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const BIOS_SIZE: usize = 16 * 1024;
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const GAMEPAK_ROM_SIZE: usize = 32 * 1024 * 1024;
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#[derive(Debug)]
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struct BiosROM(Vec<u8>);
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struct BoxedMemory(Box<[u8]>, WaitState);
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impl Bus for BiosROM {
|
||||
fn read_32(&self, addr: Addr) -> u32 {
|
||||
let addr = addr as usize;
|
||||
(&self.0[addr..addr + 4])
|
||||
.read_u32::<LittleEndian>()
|
||||
.unwrap()
|
||||
}
|
||||
#[derive(Debug)]
|
||||
struct WaitState {
|
||||
access8: usize,
|
||||
access16: usize,
|
||||
access32: usize,
|
||||
}
|
||||
|
||||
fn read_16(&self, addr: Addr) -> u16 {
|
||||
let addr = addr as usize;
|
||||
(&self.0[addr..addr + 4])
|
||||
.read_u16::<LittleEndian>()
|
||||
.unwrap()
|
||||
}
|
||||
|
||||
fn read_8(&self, addr: Addr) -> u8 {
|
||||
self.0[addr as usize]
|
||||
}
|
||||
|
||||
fn write_32(&mut self, addr: Addr, value: u32) -> Result<(), io::Error> {
|
||||
let mut wrt = io::Cursor::new(&mut self.0);
|
||||
wrt.set_position(addr as u64);
|
||||
wrt.write_u32::<LittleEndian>(value)
|
||||
}
|
||||
|
||||
fn write_16(&mut self, addr: Addr, value: u16) -> Result<(), io::Error> {
|
||||
let mut wrt = io::Cursor::new(&mut self.0);
|
||||
wrt.set_position(addr as u64);
|
||||
wrt.write_u16::<LittleEndian>(value)
|
||||
}
|
||||
|
||||
fn write_8(&mut self, addr: Addr, value: u8) -> Result<(), io::Error> {
|
||||
let mut wrt = io::Cursor::new(&mut self.0);
|
||||
wrt.write_u8(value)
|
||||
}
|
||||
|
||||
fn get_bytes(&self, addr: Addr, size: usize) -> Option<&[u8]> {
|
||||
let addr = addr as usize;
|
||||
if addr + size > self.0.len() {
|
||||
None
|
||||
} else {
|
||||
Some(&self.0[addr..addr + size])
|
||||
impl WaitState {
|
||||
fn new(access8: usize, access16: usize, access32: usize) -> WaitState {
|
||||
WaitState {
|
||||
access8,
|
||||
access16,
|
||||
access32,
|
||||
}
|
||||
}
|
||||
|
||||
fn get_cycles(&self, _addr: Addr, _access: MemoryAccess) -> usize {
|
||||
1
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Debug)]
|
||||
enum SysBusDevice {
|
||||
BiosROM(BiosROM)
|
||||
impl Default for WaitState {
|
||||
fn default() -> WaitState {
|
||||
WaitState::new(1, 1, 1)
|
||||
}
|
||||
}
|
||||
|
||||
impl Bus for BoxedMemory {
|
||||
fn get_bytes(&self, addr: Addr, size: usize) -> &[u8] {
|
||||
let addr = addr as usize;
|
||||
&self.0[addr..addr + size]
|
||||
}
|
||||
|
||||
fn get_bytes_mut(&mut self, addr: Addr, size: usize) -> &mut [u8] {
|
||||
let addr = addr as usize;
|
||||
&mut self.0[addr..addr + size]
|
||||
}
|
||||
|
||||
fn get_cycles(&self, _addr: Addr, access: MemoryAccess) -> usize {
|
||||
match access.1 {
|
||||
MemoryAccessWidth::MemoryAccess8 => self.1.access8,
|
||||
MemoryAccessWidth::MemoryAccess16 => self.1.access16,
|
||||
MemoryAccessWidth::MemoryAccess32 => self.1.access32,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Debug)]
|
||||
pub struct SysBus {
|
||||
bios: BiosROM
|
||||
bios: BoxedMemory,
|
||||
onboard_work_ram: BoxedMemory,
|
||||
internal_work_ram: BoxedMemory,
|
||||
/// Currently model the IOMem as regular buffer, later make it into something more sophisticated.
|
||||
ioregs: BoxedMemory,
|
||||
palette_ram: BoxedMemory,
|
||||
vram: BoxedMemory,
|
||||
oam: BoxedMemory,
|
||||
gamepak_flashrom: BoxedMemory,
|
||||
}
|
||||
|
||||
impl SysBus {
|
||||
pub fn new(bios_rom: Vec<u8>) -> SysBus {
|
||||
SysBus { bios: BiosROM(bios_rom) }
|
||||
}
|
||||
|
||||
fn map(&self, addr: Addr) -> & impl Bus {
|
||||
match addr as usize {
|
||||
0...BIOS_SIZE => &self.bios,
|
||||
_ => panic!("unmapped address")
|
||||
pub fn new(bios_rom: Vec<u8>, game_rom: Vec<u8>) -> SysBus {
|
||||
SysBus {
|
||||
bios: BoxedMemory(bios_rom.into_boxed_slice(), Default::default()),
|
||||
onboard_work_ram: BoxedMemory(
|
||||
vec![0; WORK_RAM_SIZE].into_boxed_slice(),
|
||||
Default::default(),
|
||||
),
|
||||
internal_work_ram: BoxedMemory(
|
||||
vec![0; INTERNAL_RAM].into_boxed_slice(),
|
||||
Default::default(),
|
||||
),
|
||||
ioregs: BoxedMemory(vec![0; 1024].into_boxed_slice(), Default::default()),
|
||||
palette_ram: BoxedMemory(
|
||||
vec![0; PALETTE_RAM_SIZE].into_boxed_slice(),
|
||||
WaitState::new(1, 1, 2),
|
||||
),
|
||||
vram: BoxedMemory(
|
||||
vec![0; VIDEO_RAM_SIZE].into_boxed_slice(),
|
||||
WaitState::new(1, 1, 2),
|
||||
),
|
||||
oam: BoxedMemory(vec![0; OAM_SIZE].into_boxed_slice(), Default::default()),
|
||||
gamepak_flashrom: BoxedMemory(game_rom.into_boxed_slice(), WaitState::new(5, 5, 8)),
|
||||
}
|
||||
}
|
||||
|
||||
fn map(&self, addr: Addr) -> &impl Bus {
|
||||
match addr as usize {
|
||||
0x0000_0000...0x0000_3fff => &self.bios,
|
||||
0x0200_0000...0x0203_ffff => &self.onboard_work_ram,
|
||||
0x0300_0000...0x0300_7fff => &self.internal_work_ram,
|
||||
0x0400_0000...0x0400_03fe => &self.ioregs,
|
||||
0x0500_0000...0x0500_03ff => &self.palette_ram,
|
||||
0x0600_0000...0x0601_7fff => &self.vram,
|
||||
0x0700_0000...0x0700_03ff => &self.oam,
|
||||
0x0800_0000...0x09ff_ffff => &self.gamepak_flashrom,
|
||||
_ => panic!("unmapped address @0x{:08x}", addr),
|
||||
}
|
||||
}
|
||||
|
||||
/// TODO proc-macro for generating this function
|
||||
fn map_mut(&mut self, addr: Addr) -> &mut impl Bus {
|
||||
match addr as usize {
|
||||
0...BIOS_SIZE => &mut self.bios,
|
||||
_ => panic!("unmapped address")
|
||||
0x0000_0000...0x0000_3fff => &mut self.bios,
|
||||
0x0200_0000...0x0203_ffff => &mut self.onboard_work_ram,
|
||||
0x0300_0000...0x0300_7fff => &mut self.internal_work_ram,
|
||||
0x0400_0000...0x0400_03fe => &mut self.ioregs,
|
||||
0x0500_0000...0x0500_03ff => &mut self.palette_ram,
|
||||
0x0600_0000...0x0601_7fff => &mut self.vram,
|
||||
0x0700_0000...0x0700_03ff => &mut self.oam,
|
||||
0x0800_0000...0x09ff_ffff => &mut self.gamepak_flashrom,
|
||||
_ => panic!("unmapped address @0x{:08x}", addr),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl Bus for SysBus {
|
||||
fn read_32(&self, addr: Addr) -> u32 {
|
||||
self.map(addr).read_32(addr)
|
||||
self.map(addr).read_32(addr & 0xff_ffff)
|
||||
}
|
||||
|
||||
fn read_16(&self, addr: Addr) -> u16 {
|
||||
self.map(addr).read_16(addr)
|
||||
self.map(addr).read_16(addr & 0xff_ffff)
|
||||
}
|
||||
|
||||
fn read_8(&self, addr: Addr) -> u8 {
|
||||
self.map(addr).read_8(addr)
|
||||
self.map(addr).read_8(addr & 0xff_ffff)
|
||||
}
|
||||
|
||||
fn write_32(&mut self, addr: Addr, value: u32) -> Result<(), io::Error> {
|
||||
self.map_mut(addr).write_32(addr, value)
|
||||
self.map_mut(addr).write_32(addr & 0xff_ffff, value)
|
||||
}
|
||||
|
||||
fn write_16(&mut self, addr: Addr, value: u16) -> Result<(), io::Error> {
|
||||
self.map_mut(addr).write_16(addr, value)
|
||||
self.map_mut(addr).write_16(addr & 0xff_ffff, value)
|
||||
}
|
||||
|
||||
fn write_8(&mut self, addr: Addr, value: u8) -> Result<(), io::Error> {
|
||||
self.map_mut(addr).write_8(addr, value)
|
||||
self.map_mut(addr).write_8(addr & 0xff_ffff, value)
|
||||
}
|
||||
|
||||
fn get_bytes(&self, addr: Addr, size: usize) -> &[u8] {
|
||||
self.map(addr).get_bytes(addr & 0xff_ffff, size)
|
||||
}
|
||||
|
||||
fn get_bytes(&self, addr: Addr, size: usize) -> Option<&[u8]> {
|
||||
self.map(addr).get_bytes(addr, size)
|
||||
fn get_bytes_mut(&mut self, addr: Addr, size: usize) -> &mut [u8] {
|
||||
self.map_mut(addr).get_bytes_mut(addr & 0xff_ffff, size)
|
||||
}
|
||||
|
||||
fn get_cycles(&self, addr: Addr, access: MemoryAccess) -> usize {
|
||||
self.map(addr).get_cycles(addr, access)
|
||||
self.map(addr).get_cycles(addr & 0xff_ffff, access)
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -7,4 +7,4 @@ pub fn read_bin_file(filename: &str) -> io::Result<Vec<u8>> {
|
|||
let mut file = File::open(filename)?;
|
||||
file.read_to_end(&mut buf)?;
|
||||
Ok(buf)
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Reference in a new issue