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fix(tests): Fix thumb t230

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THUMB 15: Base in rlist


Former-commit-id: 2516b67308e2605414f691009ce000adafda1f49
This commit is contained in:
Michel Heily 2020-01-17 13:07:26 +02:00
parent 5b90223717
commit 70c72bec2f
1 changed files with 22 additions and 14 deletions
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36
src/core/arm7tdmi/thumb/exec.rs
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@ -434,22 +434,20 @@ impl Core {
// (From GBATEK) Execution Time: nS+1N+1I (POP), (n+1)S+2N+1I (POP PC), or (n-1)S+2N (PUSH). // (From GBATEK) Execution Time: nS+1N+1I (POP), (n+1)S+2N+1I (POP PC), or (n-1)S+2N (PUSH).
let is_load = insn.is_load(); let is_load = insn.is_load();
let rb = insn.rb(); let base_reg = insn.rb();
let mut addr = self.gpr[rb] & !3; let align_preserve = self.gpr[base_reg] & 3;
let mut addr = self.gpr[base_reg] & !3;
let rlist = insn.register_list(); let rlist = insn.register_list();
self.N_cycle16(sb, self.pc); self.N_cycle16(sb, self.pc);
let mut first = true; let mut first = true;
let mut writeback = true;
if rlist != 0 { if rlist != 0 {
if is_load { if is_load {
let writeback = !rlist.bit(base_reg);
for r in 0..8 { for r in 0..8 {
if rlist.bit(r) { if rlist.bit(r) {
if r == rb { let val = sb.read_32(addr);
writeback = false;
}
let val = self.ldr_word(addr, sb);
if first { if first {
first = false; first = false;
self.add_cycle(); self.add_cycle();
@ -462,33 +460,43 @@ impl Core {
} }
} }
self.S_cycle16(sb, self.pc + 2); self.S_cycle16(sb, self.pc + 2);
if writeback {
self.gpr[base_reg] = addr + align_preserve;
}
} else { } else {
for r in 0..8 { for r in 0..8 {
if rlist.bit(r) { if rlist.bit(r) {
let v = if r != base_reg {
self.gpr[r]
} else {
if first {
addr
} else {
addr + (rlist.count_ones() - 1) * 4
}
};
if first { if first {
first = false; first = false;
} else { } else {
self.S_cycle16(sb, addr); self.S_cycle16(sb, addr);
} }
self.write_32(addr, self.gpr[r], sb); sb.write_32(addr, v);
addr += 4; addr += 4;
} }
self.gpr[base_reg] = addr + align_preserve;
} }
} }
} else { } else {
// From gbatek.htm: Empty Rlist: R15 loaded/stored (ARMv4 only), and Rb=Rb+40h (ARMv4-v5). // From gbatek.htm: Empty Rlist: R15 loaded/stored (ARMv4 only), and Rb=Rb+40h (ARMv4-v5).
if is_load { if is_load {
let val = self.ldr_word(addr, sb); let val = sb.read_32(addr);
self.set_reg(REG_PC, val & !1); self.set_reg(REG_PC, val & !1);
self.flush_pipeline16(sb); self.flush_pipeline16(sb);
} else { } else {
self.write_32(addr, self.pc + 2, sb); sb.write_32(addr, self.pc + 2);
} }
addr += 0x40; addr += 0x40;
} self.gpr[base_reg] = addr + align_preserve;
if writeback {
self.gpr[rb] = addr;
} }
Ok(()) Ok(())