Cpu: Rewrite pipeline code.
Pipeline code was unreadable up until now, this also fixes a bug: * Some roms have illegal instructions right after branch instructions, and the cpu would error trying to decode them because of pipelining. Former-commit-id: e3201c7b0d2adfc772231a3e2d5909f43c17b50f
This commit is contained in:
Michel Heily
parent
1f074e20ad
commit
7119ba2451
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@ -2,7 +2,7 @@ use crate::bit::BitIndex;
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use crate::arm7tdmi::alu::*;
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use crate::arm7tdmi::bus::Bus;
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use crate::arm7tdmi::cpu::{Core, CpuExecResult, CpuPipelineAction};
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use crate::arm7tdmi::cpu::{Core, CpuExecResult};
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use crate::arm7tdmi::exception::Exception;
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use crate::arm7tdmi::psr::RegPSR;
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use crate::arm7tdmi::{Addr, CpuError, CpuMode, CpuResult, CpuState, DecodedInstruction, REG_PC};
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@ -12,7 +12,7 @@ use super::*;
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impl Core {
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pub fn exec_arm(&mut self, bus: &mut Bus, insn: ArmInstruction) -> CpuExecResult {
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if !self.check_arm_cond(insn.cond) {
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return Ok(CpuPipelineAction::IncPC);
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return Ok(());
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}
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match insn.fmt {
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ArmFormat::BX => self.exec_bx(bus, insn),
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@ -43,8 +43,9 @@ impl Core {
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}
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self.pc = (self.pc as i32).wrapping_add(insn.branch_offset()) as u32 & !1;
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self.flush_pipeline();
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Ok(CpuPipelineAction::Flush)
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Ok(())
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}
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pub fn branch_exchange(&mut self, mut addr: Addr) -> CpuExecResult {
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@ -57,8 +58,9 @@ impl Core {
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}
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self.pc = addr;
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self.flush_pipeline();
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Ok(CpuPipelineAction::Flush)
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Ok(())
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}
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/// Cycles 2S+1N
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@ -68,7 +70,8 @@ impl Core {
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fn exec_swi(&mut self, _bus: &mut Bus, _insn: ArmInstruction) -> CpuExecResult {
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self.exception(Exception::SoftwareInterrupt);
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Ok(CpuPipelineAction::Flush)
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self.flush_pipeline();
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Ok(())
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}
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fn exec_mrs(&mut self, _bus: &mut Bus, insn: ArmInstruction) -> CpuExecResult {
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@ -83,7 +86,7 @@ impl Core {
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self.cpsr.get()
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};
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self.set_reg(insn.rd(), result);
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Ok(CpuPipelineAction::IncPC)
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Ok(())
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}
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fn exec_msr_reg(&mut self, _bus: &mut Bus, insn: ArmInstruction) -> CpuExecResult {
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@ -105,7 +108,7 @@ impl Core {
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}
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self.cpsr = new_psr;
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}
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Ok(CpuPipelineAction::IncPC)
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Ok(())
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}
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fn exec_msr_flags(&mut self, _bus: &mut Bus, insn: ArmInstruction) -> CpuExecResult {
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@ -122,7 +125,7 @@ impl Core {
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} else {
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self.cpsr.set_flag_bits(op);
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}
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Ok(CpuPipelineAction::IncPC)
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Ok(())
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}
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fn decode_operand2(&mut self, op2: BarrelShifterValue, set_flags: bool) -> CpuResult<u32> {
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@ -155,7 +158,6 @@ impl Core {
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fn exec_data_processing(&mut self, _bus: &mut Bus, insn: ArmInstruction) -> CpuExecResult {
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// TODO handle carry flag
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let mut pipeline_action = CpuPipelineAction::IncPC;
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let op1 = if insn.rn() == REG_PC {
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self.pc as i32 // prefething
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@ -186,11 +188,11 @@ impl Core {
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if let Some(result) = self.alu(opcode, op1, op2, set_flags) {
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self.set_reg(rd, result as u32);
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if rd == REG_PC {
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pipeline_action = CpuPipelineAction::Flush;
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self.flush_pipeline();
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}
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}
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Ok(pipeline_action)
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Ok(())
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}
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/// Memory Load/Store
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@ -206,7 +208,6 @@ impl Core {
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if writeback && insn.rd() == insn.rn() {
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return Err(CpuError::IllegalInstruction);
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}
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let mut pipeline_action = CpuPipelineAction::IncPC;
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let mut addr = self.get_reg(insn.rn());
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if insn.rn() == REG_PC {
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@ -236,7 +237,7 @@ impl Core {
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self.add_cycle();
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if insn.rd() == REG_PC {
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pipeline_action = CpuPipelineAction::Flush;
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self.flush_pipeline();
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}
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} else {
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let value = if insn.rd() == REG_PC {
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@ -255,7 +256,7 @@ impl Core {
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self.set_reg(insn.rn(), effective_addr as u32)
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}
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Ok(pipeline_action)
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Ok(())
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}
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fn exec_ldr_str_hs(&mut self, bus: &mut Bus, insn: ArmInstruction) -> CpuExecResult {
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@ -264,7 +265,6 @@ impl Core {
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return Err(CpuError::IllegalInstruction);
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}
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let mut pipeline_action = CpuPipelineAction::IncPC;
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let mut addr = self.get_reg(insn.rn());
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if insn.rn() == REG_PC {
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@ -296,7 +296,7 @@ impl Core {
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self.add_cycle();
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if insn.rd() == REG_PC {
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pipeline_action = CpuPipelineAction::Flush;
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self.flush_pipeline();
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}
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} else {
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let value = if insn.rd() == REG_PC {
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@ -317,7 +317,7 @@ impl Core {
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self.set_reg(insn.rn(), effective_addr as u32)
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}
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Ok(pipeline_action)
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Ok(())
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}
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fn exec_ldm_stm(&mut self, bus: &mut Bus, insn: ArmInstruction) -> CpuExecResult {
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@ -326,7 +326,6 @@ impl Core {
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let psr_user = insn.psr_and_force_user_flag();
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let is_load = insn.load_flag();
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let mut writeback = insn.write_back_flag();
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let mut pipeline_action = CpuPipelineAction::IncPC;
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let rn = insn.rn();
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let mut addr = self.gpr[rn] as i32;
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@ -357,7 +356,7 @@ impl Core {
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self.set_reg(r, val);
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if r == REG_PC {
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pipeline_action = CpuPipelineAction::Flush;
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self.flush_pipeline();
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}
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if !full {
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@ -387,7 +386,7 @@ impl Core {
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self.set_reg(rn, addr as u32);
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}
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Ok(pipeline_action)
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Ok(())
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}
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fn exec_mul_mla(&mut self, bus: &mut Bus, insn: ArmInstruction) -> CpuExecResult {
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@ -422,7 +421,7 @@ impl Core {
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self.cpsr.set_Z(result == 0);
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}
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Ok(CpuPipelineAction::IncPC)
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Ok(())
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}
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fn exec_mull_mlal(&mut self, bus: &mut Bus, insn: ArmInstruction) -> CpuExecResult {
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@ -465,6 +464,6 @@ impl Core {
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self.cpsr.set_Z(result == 0);
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}
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Ok(CpuPipelineAction::IncPC)
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Ok(())
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}
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}
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@ -374,10 +374,8 @@ mod tests {
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assert_eq!(decoded.swi_comment(), 0x1337);
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assert_eq!(format!("{}", decoded), "swi\t#0x1337");
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assert_eq!(
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core.exec_arm(&mut mem, decoded),
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Ok(CpuPipelineAction::Flush)
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);
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core.exec_arm(&mut mem, decoded).unwrap();
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assert_eq!(core.did_pipeline_flush(), true);
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assert_eq!(core.cpsr.mode(), CpuMode::Supervisor);
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assert_eq!(core.pc, Exception::SoftwareInterrupt as u32);
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@ -401,10 +399,8 @@ mod tests {
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let bytes = vec![];
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice());
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assert_eq!(
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core.exec_arm(&mut mem, decoded),
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Ok(CpuPipelineAction::Flush)
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);
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core.exec_arm(&mut mem, decoded).unwrap();
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assert_eq!(core.did_pipeline_flush(), true);
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assert_eq!(core.pc, 0x30);
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}
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@ -426,10 +422,8 @@ mod tests {
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let bytes = vec![];
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice());
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assert_eq!(
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core.exec_arm(&mut mem, decoded),
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Ok(CpuPipelineAction::Flush)
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);
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core.exec_arm(&mut mem, decoded).unwrap();
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assert_eq!(core.did_pipeline_flush(), true);
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assert_eq!(core.pc, 0x10);
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}
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@ -470,10 +464,7 @@ mod tests {
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];
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice());
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assert_eq!(
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core.exec_arm(&mut mem, decoded),
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Ok(CpuPipelineAction::IncPC)
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);
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core.exec_arm(&mut mem, decoded).unwrap();
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assert_eq!(core.gpr[2], 0x1337);
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}
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@ -514,10 +505,7 @@ mod tests {
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];
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice());
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assert_eq!(
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core.exec_arm(&mut mem, decoded),
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Ok(CpuPipelineAction::IncPC)
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);
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core.exec_arm(&mut mem, decoded).unwrap();
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assert_eq!(mem.read_32(0), 0xabababab);
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}
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@ -543,10 +531,7 @@ mod tests {
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice());
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assert_ne!(mem.read_32(core.get_reg(REG_SP) + 0x10), 0x12345678);
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assert_eq!(
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core.exec_arm(&mut mem, decoded),
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Ok(CpuPipelineAction::IncPC)
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);
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core.exec_arm(&mut mem, decoded).unwrap();
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assert_eq!(mem.read_32(core.get_reg(REG_SP) + 0x10), 0x12345678);
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}
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}
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@ -13,49 +13,16 @@ use super::{
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Addr, CpuMode, CpuResult, CpuState, DecodedInstruction, InstructionDecoder,
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};
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#[derive(Debug)]
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pub struct PipelineContext<D, N>
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where
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D: InstructionDecoder,
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N: Num,
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{
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fetched: Option<(Addr, N)>,
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decoded: Option<D>,
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#[derive(Debug, PartialEq)]
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enum PipelineState {
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Refill1,
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Refill2,
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Execute,
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}
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impl<D, N> Default for PipelineContext<D, N>
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where
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D: InstructionDecoder,
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N: Num,
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{
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fn default() -> PipelineContext<D, N> {
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PipelineContext {
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fetched: None,
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decoded: None,
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}
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}
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}
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impl<D, N> PipelineContext<D, N>
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where
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D: InstructionDecoder,
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N: Num,
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{
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pub fn flush(&mut self) {
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self.fetched = None;
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self.decoded = None;
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}
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pub fn is_flushed(&self) -> bool {
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self.fetched.is_none() && self.decoded.is_none()
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}
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pub fn is_only_fetched(&self) -> bool {
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self.fetched.is_some() && self.decoded.is_none()
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}
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pub fn is_ready_to_execute(&self) -> bool {
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self.fetched.is_some() && self.decoded.is_some()
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impl Default for PipelineState {
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fn default() -> PipelineState {
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PipelineState::Refill1
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}
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}
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@ -73,8 +40,13 @@ pub struct Core {
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pub cpsr: RegPSR,
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pub spsr: [RegPSR; 5],
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pub pipeline_arm: PipelineContext<ArmInstruction, u32>,
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pub pipeline_thumb: PipelineContext<ThumbInstruction, u16>,
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pipeline_state: PipelineState,
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fetched_arm: u32,
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decoded_arm: u32,
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fetched_thumb: u16,
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decoded_thumb: u16,
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last_executed: Option<DecodedInstruction>,
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pub cycles: usize,
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// store the gpr before executing an instruction to show diff in the Display impl
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@ -85,13 +57,7 @@ pub struct Core {
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pub verbose: bool,
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}
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#[derive(Debug, PartialEq)]
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pub enum CpuPipelineAction {
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IncPC,
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Flush,
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}
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pub type CpuExecResult = CpuResult<CpuPipelineAction>;
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pub type CpuExecResult = CpuResult<()>;
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impl Core {
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pub fn new() -> Core {
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@ -274,119 +240,110 @@ impl Core {
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}
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}
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fn step_thumb(
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&mut self,
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bus: &mut Bus,
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) -> CpuResult<(Option<DecodedInstruction>, CpuPipelineAction)> {
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fn step_arm_exec(&mut self, insn: u32, sb: &mut Bus) -> CpuResult<()> {
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let pc = self.pc;
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match self.pipeline_state {
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PipelineState::Refill1 => {
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self.pc = pc.wrapping_add(4);
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self.pipeline_state = PipelineState::Refill2;
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}
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PipelineState::Refill2 => {
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self.pc = pc.wrapping_add(4);
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self.pipeline_state = PipelineState::Execute;
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}
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PipelineState::Execute => {
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let insn = ArmInstruction::decode(insn, self.pc.wrapping_sub(8))?;
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self.gpr_previous = self.get_registers();
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self.exec_arm(sb, insn)?;
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if !self.did_pipeline_flush() {
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self.pc = pc.wrapping_add(4);
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}
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self.last_executed = Some(DecodedInstruction::Arm(insn));
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}
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}
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Ok(())
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}
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fn arm(&mut self, sb: &mut Bus) -> CpuResult<()> {
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let pc = self.pc;
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// fetch
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// let new_fetched = bus.read_16(self.pc);
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let new_fetched = self.load_16(self.pc, bus);
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let fetched_now = self.load_32(pc, sb);
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let executed_now = self.decoded_arm;
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// decode
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let new_decoded = match self.pipeline_thumb.fetched {
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Some((addr, i)) => {
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let insn = ThumbInstruction::decode(i, addr)?;
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Some(insn)
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}
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None => None,
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};
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self.decoded_arm = self.fetched_arm;
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self.fetched_arm = fetched_now;
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// exec
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let result = match self.pipeline_thumb.decoded {
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Some(d) => {
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// execute
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self.step_arm_exec(executed_now, sb)?;
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Ok(())
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}
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pub fn did_pipeline_flush(&self) -> bool {
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self.pipeline_state == PipelineState::Refill1
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}
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fn step_thumb_exec(&mut self, insn: u16, sb: &mut Bus) -> CpuResult<()> {
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let pc = self.pc;
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match self.pipeline_state {
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PipelineState::Refill1 => {
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self.pc = pc.wrapping_add(2);
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self.pipeline_state = PipelineState::Refill2;
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}
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PipelineState::Refill2 => {
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self.pc = pc.wrapping_add(2);
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self.pipeline_state = PipelineState::Execute;
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}
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PipelineState::Execute => {
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let insn = ThumbInstruction::decode(insn, self.pc.wrapping_sub(4))?;
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self.gpr_previous = self.get_registers();
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let action = self.exec_thumb(bus, d)?;
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Ok((Some(DecodedInstruction::Thumb(d)), action))
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self.exec_thumb(sb, insn)?;
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if !self.did_pipeline_flush() {
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self.pc = pc.wrapping_add(2);
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}
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None => Ok((None, CpuPipelineAction::IncPC)),
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};
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self.pipeline_thumb.fetched = Some((self.pc, new_fetched));
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if let Some(d) = new_decoded {
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self.pipeline_thumb.decoded = Some(d);
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self.last_executed = Some(DecodedInstruction::Thumb(insn));
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}
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}
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Ok(())
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}
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result
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}
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fn thumb(&mut self, sb: &mut Bus) -> CpuResult<()> {
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let pc = self.pc;
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fn step_arm(
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&mut self,
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bus: &mut Bus,
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) -> CpuResult<(Option<DecodedInstruction>, CpuPipelineAction)> {
|
||||
// let new_fetched = bus.read_32(self.pc);
|
||||
let new_fetched = self.load_32(self.pc, bus);
|
||||
// fetch
|
||||
let fetched_now = self.load_16(pc, sb);
|
||||
let executed_now = self.decoded_thumb;
|
||||
|
||||
// decode
|
||||
let new_decoded = match self.pipeline_arm.fetched {
|
||||
Some((addr, i)) => {
|
||||
let insn = ArmInstruction::decode(i, addr)?;
|
||||
Some(insn)
|
||||
}
|
||||
None => None,
|
||||
};
|
||||
self.decoded_thumb = self.fetched_thumb;
|
||||
self.fetched_thumb = fetched_now;
|
||||
|
||||
// exec
|
||||
let result = match self.pipeline_arm.decoded {
|
||||
Some(d) => {
|
||||
self.gpr_previous = self.get_registers();
|
||||
let action = self.exec_arm(bus, d)?;
|
||||
Ok((Some(DecodedInstruction::Arm(d)), action))
|
||||
}
|
||||
None => Ok((None, CpuPipelineAction::IncPC)),
|
||||
};
|
||||
|
||||
self.pipeline_arm.fetched = Some((self.pc, new_fetched));
|
||||
if let Some(d) = new_decoded {
|
||||
self.pipeline_arm.decoded = Some(d);
|
||||
// execute
|
||||
self.step_thumb_exec(executed_now, sb)?;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
result
|
||||
pub fn flush_pipeline(&mut self) {
|
||||
self.pipeline_state = PipelineState::Refill1;
|
||||
}
|
||||
|
||||
/// Perform a pipeline step
|
||||
/// If an instruction was executed in this step, return it.
|
||||
pub fn step(&mut self, bus: &mut Bus) -> CpuResult<Option<DecodedInstruction>> {
|
||||
let (executed_instruction, pipeline_action) = match self.cpsr.state() {
|
||||
CpuState::ARM => self.step_arm(bus),
|
||||
CpuState::THUMB => self.step_thumb(bus),
|
||||
}?;
|
||||
|
||||
match pipeline_action {
|
||||
CpuPipelineAction::IncPC => self.advance_pc(),
|
||||
CpuPipelineAction::Flush => {
|
||||
self.pipeline_arm.flush();
|
||||
self.pipeline_thumb.flush();
|
||||
pub fn step(&mut self, bus: &mut Bus) -> CpuResult<()> {
|
||||
match self.cpsr.state() {
|
||||
CpuState::ARM => self.arm(bus),
|
||||
CpuState::THUMB => self.thumb(bus),
|
||||
}
|
||||
}
|
||||
|
||||
Ok(executed_instruction)
|
||||
}
|
||||
|
||||
/// Get's the address of the next instruction that is going to be executed
|
||||
pub fn get_next_pc(&self) -> Addr {
|
||||
match self.cpsr.state() {
|
||||
CpuState::ARM => {
|
||||
if self.pipeline_arm.is_flushed() {
|
||||
self.pc as Addr
|
||||
} else if self.pipeline_arm.is_only_fetched() {
|
||||
self.pipeline_arm.fetched.unwrap().0
|
||||
} else if self.pipeline_arm.is_ready_to_execute() {
|
||||
self.pipeline_arm.decoded.unwrap().pc
|
||||
} else {
|
||||
unreachable!()
|
||||
}
|
||||
}
|
||||
CpuState::THUMB => {
|
||||
if self.pipeline_thumb.is_flushed() {
|
||||
self.pc as Addr
|
||||
} else if self.pipeline_thumb.is_only_fetched() {
|
||||
self.pipeline_thumb.fetched.unwrap().0
|
||||
} else if self.pipeline_thumb.is_ready_to_execute() {
|
||||
self.pipeline_thumb.decoded.unwrap().pc
|
||||
} else {
|
||||
unreachable!()
|
||||
}
|
||||
}
|
||||
let insn_size = self.word_size() as u32;
|
||||
match self.pipeline_state {
|
||||
PipelineState::Refill1 => self.pc,
|
||||
PipelineState::Refill2 => self.pc - insn_size,
|
||||
PipelineState::Execute => self.pc - 2 * insn_size,
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -395,8 +352,14 @@ impl Core {
|
|||
/// and the address of the next instruction to be executed;
|
||||
pub fn step_one(&mut self, bus: &mut Bus) -> CpuResult<DecodedInstruction> {
|
||||
loop {
|
||||
if let Some(i) = self.step(bus)? {
|
||||
return Ok(i);
|
||||
match self.pipeline_state {
|
||||
PipelineState::Execute => {
|
||||
self.step(bus)?;
|
||||
return Ok(self.last_executed.unwrap());
|
||||
}
|
||||
_ => {
|
||||
self.step(bus)?;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -49,7 +49,6 @@ impl Core {
|
|||
|
||||
// Set PC to vector address
|
||||
self.pc = vector;
|
||||
self.pipeline_arm.flush();
|
||||
self.pipeline_thumb.flush();
|
||||
self.flush_pipeline();
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
use crate::arm7tdmi::bus::Bus;
|
||||
use crate::arm7tdmi::cpu::{Core, CpuExecResult, CpuPipelineAction};
|
||||
use crate::arm7tdmi::cpu::{Core, CpuExecResult};
|
||||
use crate::arm7tdmi::*;
|
||||
|
||||
use super::*;
|
||||
|
|
@ -35,7 +35,7 @@ impl Core {
|
|||
self.set_reg(rd, result as u32);
|
||||
}
|
||||
|
||||
Ok(CpuPipelineAction::IncPC)
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn exec_thumb_add_sub(&mut self, _bus: &mut Bus, insn: ThumbInstruction) -> CpuExecResult {
|
||||
|
|
@ -56,7 +56,7 @@ impl Core {
|
|||
self.set_reg(insn.rd(), result as u32);
|
||||
}
|
||||
|
||||
Ok(CpuPipelineAction::IncPC)
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn exec_thumb_data_process_imm(
|
||||
|
|
@ -72,7 +72,7 @@ impl Core {
|
|||
self.set_reg(insn.rd(), result as u32);
|
||||
}
|
||||
|
||||
Ok(CpuPipelineAction::IncPC)
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn exec_thumb_mul(&mut self, _bus: &mut Bus, insn: ThumbInstruction) -> CpuExecResult {
|
||||
|
|
@ -83,7 +83,7 @@ impl Core {
|
|||
self.add_cycle();
|
||||
}
|
||||
self.gpr[insn.rd()] = op1.wrapping_mul(op2) as u32;
|
||||
Ok(CpuPipelineAction::IncPC)
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn exec_thumb_alu_ops(&mut self, _bus: &mut Bus, insn: ThumbInstruction) -> CpuExecResult {
|
||||
|
|
@ -102,7 +102,7 @@ impl Core {
|
|||
self.set_reg(rd, result as u32);
|
||||
}
|
||||
|
||||
Ok(CpuPipelineAction::IncPC)
|
||||
Ok(())
|
||||
}
|
||||
|
||||
/// Cycles 2S+1N
|
||||
|
|
@ -141,10 +141,10 @@ impl Core {
|
|||
if let Some(result) = result {
|
||||
self.set_reg(dst_reg, result as u32);
|
||||
if dst_reg == REG_PC {
|
||||
return Ok(CpuPipelineAction::Flush);
|
||||
self.flush_pipeline();
|
||||
}
|
||||
}
|
||||
Ok(CpuPipelineAction::IncPC)
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -156,7 +156,7 @@ impl Core {
|
|||
// +1I
|
||||
self.add_cycle();
|
||||
|
||||
Ok(CpuPipelineAction::IncPC)
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn do_exec_thumb_ldr_str(
|
||||
|
|
@ -185,7 +185,7 @@ impl Core {
|
|||
};
|
||||
}
|
||||
|
||||
Ok(CpuPipelineAction::IncPC)
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn exec_thumb_ldr_str_reg_offset(
|
||||
|
|
@ -232,7 +232,7 @@ impl Core {
|
|||
}
|
||||
}
|
||||
|
||||
Ok(CpuPipelineAction::IncPC)
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn exec_thumb_ldr_str_imm_offset(
|
||||
|
|
@ -263,7 +263,7 @@ impl Core {
|
|||
} else {
|
||||
self.store_16(addr, self.gpr[insn.rd()] as u16, bus);
|
||||
}
|
||||
Ok(CpuPipelineAction::IncPC)
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn exec_thumb_ldr_str_sp(&mut self, bus: &mut Bus, insn: ThumbInstruction) -> CpuExecResult {
|
||||
|
|
@ -279,7 +279,7 @@ impl Core {
|
|||
};
|
||||
self.gpr[insn.rd()] = result;
|
||||
|
||||
Ok(CpuPipelineAction::IncPC)
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn do_exec_thumb_ldr_str_with_addr(
|
||||
|
|
@ -295,7 +295,7 @@ impl Core {
|
|||
} else {
|
||||
self.store_32(addr, self.gpr[insn.rd()], bus);
|
||||
}
|
||||
Ok(CpuPipelineAction::IncPC)
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn exec_thumb_add_sp(&mut self, _bus: &mut Bus, insn: ThumbInstruction) -> CpuExecResult {
|
||||
|
|
@ -308,14 +308,13 @@ impl Core {
|
|||
self.gpr[REG_SP] = result as u32;
|
||||
}
|
||||
|
||||
Ok(CpuPipelineAction::IncPC)
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn exec_thumb_push_pop(&mut self, bus: &mut Bus, insn: ThumbInstruction) -> CpuExecResult {
|
||||
// (From GBATEK) Execution Time: nS+1N+1I (POP), (n+1)S+2N+1I (POP PC), or (n-1)S+2N (PUSH).
|
||||
|
||||
let is_pop = insn.is_load();
|
||||
let mut pipeline_action = CpuPipelineAction::IncPC;
|
||||
|
||||
let pc_lr_flag = insn.flag(ThumbInstruction::FLAG_R);
|
||||
let rlist = insn.register_list();
|
||||
|
|
@ -326,7 +325,7 @@ impl Core {
|
|||
if pc_lr_flag {
|
||||
pop(self, bus, REG_PC);
|
||||
self.pc = self.pc & !1;
|
||||
pipeline_action = CpuPipelineAction::Flush;
|
||||
self.flush_pipeline();
|
||||
}
|
||||
self.add_cycle();
|
||||
} else {
|
||||
|
|
@ -338,7 +337,7 @@ impl Core {
|
|||
}
|
||||
}
|
||||
|
||||
Ok(pipeline_action)
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn exec_thumb_ldm_stm(&mut self, bus: &mut Bus, insn: ThumbInstruction) -> CpuExecResult {
|
||||
|
|
@ -365,7 +364,7 @@ impl Core {
|
|||
|
||||
self.gpr[rb] = addr as u32;
|
||||
|
||||
Ok(CpuPipelineAction::IncPC)
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn exec_thumb_branch_with_cond(
|
||||
|
|
@ -374,18 +373,20 @@ impl Core {
|
|||
insn: ThumbInstruction,
|
||||
) -> CpuExecResult {
|
||||
if !self.check_arm_cond(insn.cond()) {
|
||||
Ok(CpuPipelineAction::IncPC)
|
||||
Ok(())
|
||||
} else {
|
||||
let offset = ((insn.offset8() as i8) << 1) as i32;
|
||||
self.pc = (self.pc as i32).wrapping_add(offset) as u32;
|
||||
Ok(CpuPipelineAction::Flush)
|
||||
self.flush_pipeline();
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
fn exec_thumb_branch(&mut self, _bus: &mut Bus, insn: ThumbInstruction) -> CpuExecResult {
|
||||
let offset = ((insn.offset11() << 21) >> 20) as i32;
|
||||
self.pc = (self.pc as i32).wrapping_add(offset) as u32;
|
||||
Ok(CpuPipelineAction::Flush)
|
||||
self.flush_pipeline();
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn exec_thumb_branch_long_with_link(
|
||||
|
|
@ -400,12 +401,13 @@ impl Core {
|
|||
self.pc = (self.gpr[REG_LR] as i32).wrapping_add(off) as u32;
|
||||
self.gpr[REG_LR] = next_pc;
|
||||
|
||||
Ok(CpuPipelineAction::Flush)
|
||||
self.flush_pipeline();
|
||||
Ok(())
|
||||
} else {
|
||||
off = (off << 21) >> 9;
|
||||
self.gpr[REG_LR] = (self.pc as i32).wrapping_add(off) as u32;
|
||||
|
||||
Ok(CpuPipelineAction::IncPC)
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -355,17 +355,11 @@ impl ThumbInstruction {
|
|||
/// All instructions constants were generated using an ARM assembler.
|
||||
mod tests {
|
||||
use super::*;
|
||||
use crate::arm7tdmi::{
|
||||
cpu::{Core, CpuPipelineAction},
|
||||
Bus,
|
||||
};
|
||||
use crate::arm7tdmi::{Core, Bus};
|
||||
use crate::sysbus::BoxedMemory;
|
||||
|
||||
#[test]
|
||||
fn mov_low_reg() {
|
||||
use crate::arm7tdmi::cpu::{Core, CpuPipelineAction};
|
||||
use crate::sysbus::BoxedMemory;
|
||||
|
||||
let bytes = vec![];
|
||||
let mut mem = BoxedMemory::new(bytes.into_boxed_slice());
|
||||
let mut core = Core::new();
|
||||
|
|
@ -375,10 +369,7 @@ mod tests {
|
|||
let insn = ThumbInstruction::decode(0x2027, 0).unwrap();
|
||||
|
||||
assert_eq!(format!("{}", insn), "mov\tr0, #0x27");
|
||||
assert_eq!(
|
||||
core.exec_thumb(&mut mem, insn),
|
||||
Ok(CpuPipelineAction::IncPC)
|
||||
);
|
||||
core.exec_thumb(&mut mem, insn).unwrap();
|
||||
assert_eq!(core.get_reg(0), 0x27);
|
||||
}
|
||||
|
||||
|
|
@ -407,10 +398,7 @@ mod tests {
|
|||
core.set_reg(0, 0);
|
||||
|
||||
assert_eq!(format!("{}", insn), "ldr\tr0, [pc, #0x4] ; = #0xc");
|
||||
assert_eq!(
|
||||
core.exec_thumb(&mut mem, insn),
|
||||
Ok(CpuPipelineAction::IncPC)
|
||||
);
|
||||
core.exec_thumb(&mut mem, insn).unwrap();
|
||||
assert_eq!(core.get_reg(0), 0x12345678);
|
||||
}
|
||||
|
||||
|
|
@ -439,15 +427,9 @@ mod tests {
|
|||
|
||||
assert_eq!(format!("{}", str_insn), "str\tr0, [r4, r1]");
|
||||
assert_eq!(format!("{}", ldr_insn), "ldrb\tr2, [r4, r1]");
|
||||
assert_eq!(
|
||||
core.exec_thumb(&mut mem, str_insn),
|
||||
Ok(CpuPipelineAction::IncPC)
|
||||
);
|
||||
core.exec_thumb(&mut mem, str_insn).unwrap();
|
||||
assert_eq!(mem.read_32(0x10), 0x12345678);
|
||||
assert_eq!(
|
||||
core.exec_thumb(&mut mem, ldr_insn),
|
||||
Ok(CpuPipelineAction::IncPC)
|
||||
);
|
||||
core.exec_thumb(&mut mem, ldr_insn).unwrap();
|
||||
assert_eq!(core.get_reg(2), 0x78);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -3,9 +3,9 @@
|
|||
use super::arm7tdmi::{exception::*, Core, DecodedInstruction};
|
||||
use super::cartridge::Cartridge;
|
||||
use super::dma::DmaChannel;
|
||||
use super::gpu::*;
|
||||
use super::interrupt::*;
|
||||
use super::ioregs::consts::*;
|
||||
use super::gpu::*;
|
||||
use super::sysbus::SysBus;
|
||||
|
||||
use super::{EmuIoDev, GBAError, GBAResult};
|
||||
|
|
|
|||
|
|
@ -15,10 +15,10 @@ extern crate ansi_term;
|
|||
extern crate colored; // not needed in Rust 2018
|
||||
|
||||
pub mod arm7tdmi;
|
||||
pub mod gpu;
|
||||
pub mod cartridge;
|
||||
pub mod debugger;
|
||||
pub mod disass;
|
||||
pub mod gpu;
|
||||
pub mod sysbus;
|
||||
pub use sysbus::SysBus;
|
||||
pub mod interrupt;
|
||||
|
|
|
|||
Reference in a new issue