From 71a4837d2564adc9f4523b00d2dd4e704ae50a0c Mon Sep 17 00:00:00 2001 From: Michel Heily Date: Tue, 31 Dec 2019 21:18:28 +0200 Subject: [PATCH] core: Reduce overhead in Bus interface Former-commit-id: 1b3b00825d0b6aec0223445a1f00408397efca56 --- src/core/bus.rs | 23 +++++++++++++++++++---- src/core/cartridge.rs | 28 ++-------------------------- src/core/dma.rs | 2 +- src/core/iodev.rs | 9 --------- src/core/sysbus.rs | 38 -------------------------------------- 5 files changed, 22 insertions(+), 78 deletions(-) diff --git a/src/core/bus.rs b/src/core/bus.rs index 3a2dc0b..622b53c 100644 --- a/src/core/bus.rs +++ b/src/core/bus.rs @@ -1,11 +1,26 @@ pub type Addr = u32; pub trait Bus { - fn read_32(&self, addr: Addr) -> u32; - fn read_16(&self, addr: Addr) -> u16; + fn read_32(&self, addr: Addr) -> u32 { + self.read_16(addr) as u32 | (self.read_16(addr + 2) as u32) << 16 + } + + fn read_16(&self, addr: Addr) -> u16 { + self.read_8(addr) as u16 | (self.read_8(addr + 1) as u16) << 8 + } + fn read_8(&self, addr: Addr) -> u8; - fn write_32(&mut self, addr: Addr, value: u32); - fn write_16(&mut self, addr: Addr, value: u16); + + fn write_32(&mut self, addr: Addr, value: u32) { + self.write_16(addr, (value & 0xffff) as u16); + self.write_16(addr + 2, (value >> 16) as u16); + } + + fn write_16(&mut self, addr: Addr, value: u16) { + self.write_8(addr, (value & 0xff) as u8); + self.write_8(addr + 1, ((value >> 8) & 0xff) as u8); + } + fn write_8(&mut self, addr: Addr, value: u8); fn get_bytes(&self, range: std::ops::Range) -> Vec { diff --git a/src/core/cartridge.rs b/src/core/cartridge.rs index 3ac6a0d..96c3d6b 100644 --- a/src/core/cartridge.rs +++ b/src/core/cartridge.rs @@ -123,35 +123,11 @@ impl Cartridge { } impl Bus for Cartridge { - fn read_32(&self, addr: Addr) -> u32 { - (&self.bytes[addr as usize..]) - .read_u32::() - .unwrap() - } - - fn read_16(&self, addr: Addr) -> u16 { - (&self.bytes[addr as usize..]) - .read_u16::() - .unwrap() - } - fn read_8(&self, addr: Addr) -> u8 { - (&self.bytes[addr as usize..])[0] - } - - fn write_32(&mut self, addr: Addr, value: u32) { - (&mut self.bytes[addr as usize..]) - .write_u32::(value) - .unwrap() - } - - fn write_16(&mut self, addr: Addr, value: u16) { - (&mut self.bytes[addr as usize..]) - .write_u16::(value) - .unwrap() + self.bytes[addr as usize] } fn write_8(&mut self, addr: Addr, value: u8) { - (&mut self.bytes[addr as usize..]).write_u8(value).unwrap() + self.bytes[addr as usize] = value; } } diff --git a/src/core/dma.rs b/src/core/dma.rs index 2d795f9..71a3f3a 100644 --- a/src/core/dma.rs +++ b/src/core/dma.rs @@ -221,7 +221,7 @@ impl DmaController { self.pending_bittset.remove(channel_id); } } - _ => panic!("Invalid dma offset"), + _ => panic!("Invalid dma offset {:x}", ofs), } } diff --git a/src/core/iodev.rs b/src/core/iodev.rs index beb4dd5..5dcf7ab 100644 --- a/src/core/iodev.rs +++ b/src/core/iodev.rs @@ -49,10 +49,6 @@ impl IoDevices { } impl Bus for IoDevices { - fn read_32(&self, addr: Addr) -> u32 { - (self.read_16(addr + 2) as u32) << 16 | (self.read_16(addr) as u32) - } - fn read_16(&self, addr: Addr) -> u16 { let io = self; let io_addr = addr + IO_BASE; @@ -118,11 +114,6 @@ impl Bus for IoDevices { } } - fn write_32(&mut self, addr: Addr, value: u32) { - self.write_16(addr, (value & 0xffff) as u16); - self.write_16(addr + 2, (value >> 16) as u16); - } - fn write_16(&mut self, addr: Addr, value: u16) { let mut io = self; if addr > 0x0800 { diff --git a/src/core/sysbus.rs b/src/core/sysbus.rs index 8a5ee91..be32f33 100644 --- a/src/core/sysbus.rs +++ b/src/core/sysbus.rs @@ -1,8 +1,6 @@ use std::fmt; use std::ops::Add; -use byteorder::{LittleEndian, ReadBytesExt, WriteBytesExt}; - use super::cartridge::Cartridge; use super::gpu::{GpuState, VIDEO_RAM_SIZE}; use super::iodev::IoDevices; @@ -78,28 +76,10 @@ impl BoxedMemory { } impl Bus for BoxedMemory { - fn read_32(&self, addr: Addr) -> u32 { - self.read_16(addr) as u32 | (self.read_16(addr + 2) as u32) << 16 - } - - fn read_16(&self, addr: Addr) -> u16 { - self.read_8(addr) as u16 | (self.read_8(addr+1) as u16) << 8 - } - fn read_8(&self, addr: Addr) -> u8 { self.mem[addr as usize] } - fn write_32(&mut self, addr: Addr, value: u32) { - self.write_16(addr, (value & 0xffff) as u16); - self.write_16(addr + 2, (value >> 16) as u16); - } - - fn write_16(&mut self, addr: Addr, value: u16) { - self.write_8(addr, (value & 0xff) as u8); - self.write_8(addr + 1, ((value >> 8) & 0xff) as u8); - } - fn write_8(&mut self, addr: Addr, value: u8) { self.mem[addr as usize] = value; } @@ -109,22 +89,10 @@ impl Bus for BoxedMemory { struct DummyBus([u8; 4]); impl Bus for DummyBus { - fn read_32(&self, _addr: Addr) -> u32 { - 0 - } - - fn read_16(&self, _addr: Addr) -> u16 { - 0 - } - fn read_8(&self, _addr: Addr) -> u8 { 0 } - fn write_32(&mut self, _addr: Addr, _value: u32) {} - - fn write_16(&mut self, _addr: Addr, _value: u16) {} - fn write_8(&mut self, _addr: Addr, _value: u8) {} } @@ -275,17 +243,11 @@ impl Bus for SysBus { } fn read_16(&self, addr: Addr) -> u16 { - if self.trace_access { - println!("[TRACE] read_32 addr={:x}", addr); - } let (dev, addr) = self.map(addr); dev.read_16(addr & 0x1ff_fffe) } fn read_8(&self, addr: Addr) -> u8 { - if self.trace_access { - println!("[TRACE] read_32 addr={:x}", addr); - } let (dev, addr) = self.map(addr); dev.read_8(addr & 0x1ff_ffff) }