From 74329c2a0b6fde08389476ae43eaa181fe5234e7 Mon Sep 17 00:00:00 2001 From: Michel Heily Date: Fri, 5 Jul 2019 16:10:21 +0300 Subject: [PATCH] Never leave unfinished work.. Former-commit-id: 91acecdaf3ec7f9de892bd9f712e3cf521e08beb --- src/arm7tdmi/thumb/exec.rs | 20 ++++++++++++++++++-- src/arm7tdmi/thumb/mod.rs | 2 +- 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/src/arm7tdmi/thumb/exec.rs b/src/arm7tdmi/thumb/exec.rs index 41961b7..1090c45 100644 --- a/src/arm7tdmi/thumb/exec.rs +++ b/src/arm7tdmi/thumb/exec.rs @@ -121,8 +121,24 @@ impl Core { if OpFormat5::BX == insn.format5_op() { self.exec_thumb_bx(bus, insn) } else { - unimplemented!("Sorry, I'm tired"); - // Ok(CpuPipelineAction::IncPC) + let dst_reg = if insn.flag(ThumbInstruction::FLAG_H1) { + insn.rd() + 8 + } else { + insn.rd() + }; + let src_reg = if insn.flag(ThumbInstruction::FLAG_H2) { + insn.rs() + 8 + } else { + insn.rs() + }; + let arm_alu_op: ArmOpCode = insn.format5_op().into(); + let op1 = self.gpr[dst_reg] as i32; + let op2 = self.gpr[src_reg] as i32; + let result = self.alu(arm_alu_op, op1, op2, true); + if let Some(result) = result { + self.gpr[dst_reg] = result as u32; + } + Ok(CpuPipelineAction::IncPC) } } diff --git a/src/arm7tdmi/thumb/mod.rs b/src/arm7tdmi/thumb/mod.rs index 1355b38..08b49f3 100644 --- a/src/arm7tdmi/thumb/mod.rs +++ b/src/arm7tdmi/thumb/mod.rs @@ -188,7 +188,7 @@ impl From for ArmOpCode { OpFormat5::ADD => ArmOpCode::ADD, OpFormat5::CMP => ArmOpCode::CMP, OpFormat5::MOV => ArmOpCode::MOV, - _ => unreachable!(), // this should not be called if op = BX + OpFormat5::BX => panic!("this should not be called if op = BX") } } }