More const generics..
Former-commit-id: 74e4c88128d8c83bbb23a874ba8e0821ffc583a7 Former-commit-id: 99ed5c5f73ba9ad2e95b9b190e0100d0e1b9e6a2
This commit is contained in:
parent
0665ff7451
commit
892dfbe395
160
core/build.rs
160
core/build.rs
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@ -7,47 +7,83 @@ extern crate bit;
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use bit::BitIndex;
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// copied and slightly adjusted from src/core/arm7tdmi/thumb/mod.rs
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fn thumb_decode(i: u16) -> &'static str {
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fn thumb_decode(i: u16) -> (&'static str, String) {
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if i & 0xf800 == 0x1800 {
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"AddSub"
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(
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"AddSub",
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format!(
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"exec_thumb_add_sub::<{SUB}, {IMM}, {RN}>",
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SUB = i.bit(9),
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IMM = i.bit(10),
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RN = i.bit_range(6..9) as usize
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),
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)
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} else if i & 0xe000 == 0x0000 {
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"MoveShiftedReg"
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(
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"MoveShiftedReg",
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format!(
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"exec_thumb_move_shifted_reg::<{BS_OP}, {OFFSET5}>",
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BS_OP = i.bit_range(11..13) as u8,
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OFFSET5 = i.bit_range(6..11) as u8
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),
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)
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} else if i & 0xe000 == 0x2000 {
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"DataProcessImm"
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(
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"DataProcessImm",
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String::from("exec_thumb_data_process_imm"),
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)
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} else if i & 0xfc00 == 0x4000 {
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"AluOps"
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("AluOps", String::from("exec_thumb_alu_ops"))
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} else if i & 0xfc00 == 0x4400 {
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"HiRegOpOrBranchExchange"
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(
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"HiRegOpOrBranchExchange",
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String::from("exec_thumb_hi_reg_op_or_bx"),
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)
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} else if i & 0xf800 == 0x4800 {
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"LdrPc"
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("LdrPc", String::from("exec_thumb_ldr_pc"))
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} else if i & 0xf200 == 0x5000 {
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"LdrStrRegOffset"
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(
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"LdrStrRegOffset",
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String::from("exec_thumb_ldr_str_reg_offset"),
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)
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} else if i & 0xf200 == 0x5200 {
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"LdrStrSHB"
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("LdrStrSHB", String::from("exec_thumb_ldr_str_shb"))
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} else if i & 0xe000 == 0x6000 {
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"LdrStrImmOffset"
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(
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"LdrStrImmOffset",
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String::from("exec_thumb_ldr_str_imm_offset"),
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)
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} else if i & 0xf000 == 0x8000 {
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"LdrStrHalfWord"
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(
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"LdrStrHalfWord",
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String::from("exec_thumb_ldr_str_halfword"),
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)
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} else if i & 0xf000 == 0x9000 {
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"LdrStrSp"
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("LdrStrSp", String::from("exec_thumb_ldr_str_sp"))
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} else if i & 0xf000 == 0xa000 {
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"LoadAddress"
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("LoadAddress", String::from("exec_thumb_load_address"))
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} else if i & 0xff00 == 0xb000 {
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"AddSp"
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("AddSp", String::from("exec_thumb_add_sp"))
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} else if i & 0xf600 == 0xb400 {
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"PushPop"
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("PushPop", String::from("exec_thumb_push_pop"))
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} else if i & 0xf000 == 0xc000 {
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"LdmStm"
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("LdmStm", String::from("exec_thumb_ldm_stm"))
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} else if i & 0xff00 == 0xdf00 {
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"Swi"
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("Swi", String::from("exec_thumb_swi"))
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} else if i & 0xf000 == 0xd000 {
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"BranchConditional"
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(
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"BranchConditional",
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String::from("exec_thumb_branch_with_cond"),
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)
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} else if i & 0xf800 == 0xe000 {
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"Branch"
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("Branch", String::from("exec_thumb_branch"))
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} else if i & 0xf000 == 0xf000 {
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"BranchLongWithLink"
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(
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"BranchLongWithLink",
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String::from("exec_thumb_branch_long_with_link"),
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)
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} else {
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"Undefined"
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("Undefined", String::from("thumb_undefined"))
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}
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}
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@ -98,7 +134,7 @@ impl BitAsInt<u32> for u32 {}
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/// |_Cond__|1_1_1_0|CPopc|L|__CRn__|__Rd___|__CP#__|_CP__|1|__CRm__| CoRegTrans
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/// |_Cond__|1_1_1_1|_____________Ignored_by_Processor______________| SWI
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/// ```
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fn arm_decode(i: u32) -> String {
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fn arm_decode(i: u32) -> (&'static str, String) {
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const T: bool = true;
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const F: bool = false;
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@ -107,25 +143,25 @@ fn arm_decode(i: u32) -> String {
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0b00 => {
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/* DataProcessing and friends */
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let result: Option<String> = match (i.bit_range(23..26), i.bit_range(4..8)) {
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let result = match (i.bit_range(23..26), i.bit_range(4..8)) {
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(0b000, 0b1001) => {
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if 0b0 == i.ibit(22) {
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Some(String::from("exec_arm_mul_mla"))
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Some(("Multiply", String::from("exec_arm_mul_mla")))
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} else {
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None
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}
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}
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(0b001, 0b1001) => Some(String::from("exec_arm_mull_mlal")),
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(0b001, 0b1001) => Some(("MultiplyLong", String::from("exec_arm_mull_mlal"))),
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(0b010, 0b1001) => {
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if 0b00 == i.bit_range(20..22) {
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Some(String::from("exec_arm_swp"))
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Some(("SingleDataSwap", String::from("exec_arm_swp")))
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} else {
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None
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}
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}
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(0b010, 0b0001) => {
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if 0b010 == i.bit_range(20..23) {
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Some(format!("exec_arm_bx"))
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Some(("BranchExchange", format!("exec_arm_bx")))
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} else {
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None
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}
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@ -135,8 +171,8 @@ fn arm_decode(i: u32) -> String {
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result.unwrap_or_else(|| {
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match (i.ibit(25), i.ibit(22), i.ibit(7), i.ibit(4)) {
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(0, 0, 1, 1) => String::from("exec_arm_ldr_str_hs_reg"),
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(0, 1, 1, 1) => String::from("exec_arm_ldr_str_hs_imm"),
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(0, 0, 1, 1) => ("HalfwordDataTransferRegOffset", String::from("exec_arm_ldr_str_hs_reg")),
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(0, 1, 1, 1) => ("HalfwordDataTransferImmediateOffset", String::from("exec_arm_ldr_str_hs_imm")),
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_ => {
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let set_cond_flags = i.bit(20);
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// PSR Transfers are encoded as a subset of Data Processing,
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@ -145,16 +181,16 @@ fn arm_decode(i: u32) -> String {
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if !set_cond_flags && is_op_not_touching_rd {
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if i.bit(21) {
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// Since bit-16 is ignored and we can't know statically if this is a exec_arm_transfer_to_status or exec_arm_transfer_to_status
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String::from("exec_arm_transfer_to_status")
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("MoveToStatus", String::from("exec_arm_transfer_to_status"))
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} else {
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String::from("exec_arm_mrs")
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("MoveFromStatus", String::from("exec_arm_mrs"))
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}
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} else {
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format!("exec_arm_data_processing::<{OP}, {IMM}, {SET_FLAGS}, {SHIFT_BY_REG}>",
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("DataProcessing", format!("exec_arm_data_processing::<{OP}, {IMM}, {SET_FLAGS}, {SHIFT_BY_REG}>",
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OP=i.bit_range(21..25),
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IMM=i.bit(25),
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SET_FLAGS=i.bit(20),
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SHIFT_BY_REG=i.bit(4))
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SHIFT_BY_REG=i.bit(4)))
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}
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}
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}
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@ -162,7 +198,7 @@ fn arm_decode(i: u32) -> String {
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}
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0b01 => {
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match (i.bit(25), i.bit(4)) {
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(_, F) | (F, T) => format!(
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(_, F) | (F, T) => ("SingleDataTransfer", format!(
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"exec_arm_ldr_str::<{LOAD}, {WRITEBACK}, {PRE_INDEX}, {BYTE}, {SHIFT}, {ADD}, {BS_OP}, {SHIFT_BY_REG}>",
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LOAD = i.bit(20),
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WRITEBACK = i.bit(21),
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@ -172,53 +208,30 @@ fn arm_decode(i: u32) -> String {
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SHIFT = i.bit(25),
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BS_OP = i.bit_range(5..7) as u8,
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SHIFT_BY_REG = i.bit(4),
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),
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(T, T) => String::from("arm_undefined"), /* Possible ARM11 but we don't implement these */
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)),
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(T, T) => ("Undefined", String::from("arm_undefined")), /* Possible ARM11 but we don't implement these */
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}
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}
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0b10 => match i.bit(25) {
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F => String::from("exec_arm_ldm_stm"),
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T => format!("exec_arm_b_bl::<{LINK}>", LINK = i.bit(24)),
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F => ("BlockDataTransfer", String::from("exec_arm_ldm_stm")),
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T => (
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"BranchLink",
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format!("exec_arm_b_bl::<{LINK}>", LINK = i.bit(24)),
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),
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},
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0b11 => {
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match (i.ibit(25), i.ibit(24), i.ibit(4)) {
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(0b0, _, _) => String::from("arm_undefined"), /* CoprocessorDataTransfer not implemented */
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(0b1, 0b0, 0b0) => String::from("arm_undefined"), /* CoprocessorDataOperation not implemented */
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(0b1, 0b0, 0b1) => String::from("arm_undefined"), /* CoprocessorRegisterTransfer not implemented */
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(0b1, 0b1, _) => String::from("exec_arm_swi"),
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_ => String::from("arm_undefined"),
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(0b0, _, _) => ("Undefined", String::from("arm_undefined")), /* CoprocessorDataTransfer not implemented */
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(0b1, 0b0, 0b0) => ("Undefined", String::from("arm_undefined")), /* CoprocessorDataOperation not implemented */
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(0b1, 0b0, 0b1) => ("Undefined", String::from("arm_undefined")), /* CoprocessorRegisterTransfer not implemented */
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(0b1, 0b1, _) => ("SoftwareInterrupt", String::from("exec_arm_swi")),
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_ => ("Undefined", String::from("arm_undefined")),
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}
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}
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_ => unreachable!(),
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}
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}
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fn thumb_format_to_handler(thumb_fmt: &str) -> &'static str {
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match thumb_fmt {
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"MoveShiftedReg" => "exec_thumb_move_shifted_reg",
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"AddSub" => "exec_thumb_add_sub",
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"DataProcessImm" => "exec_thumb_data_process_imm",
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"AluOps" => "exec_thumb_alu_ops",
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"HiRegOpOrBranchExchange" => "exec_thumb_hi_reg_op_or_bx",
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"LdrPc" => "exec_thumb_ldr_pc",
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"LdrStrRegOffset" => "exec_thumb_ldr_str_reg_offset",
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"LdrStrSHB" => "exec_thumb_ldr_str_shb",
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"LdrStrImmOffset" => "exec_thumb_ldr_str_imm_offset",
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"LdrStrHalfWord" => "exec_thumb_ldr_str_halfword",
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"LdrStrSp" => "exec_thumb_ldr_str_sp",
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"LoadAddress" => "exec_thumb_load_address",
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"AddSp" => "exec_thumb_add_sp",
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"PushPop" => "exec_thumb_push_pop",
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"LdmStm" => "exec_thumb_ldm_stm",
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"BranchConditional" => "exec_thumb_branch_with_cond",
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"Swi" => "exec_thumb_swi",
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"Branch" => "exec_thumb_branch",
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"BranchLongWithLink" => "exec_thumb_branch_long_with_link",
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"Undefined" => "thumb_undefined",
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_ => unreachable!(),
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}
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}
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fn generate_thumb_lut(file: &mut fs::File) -> Result<(), std::io::Error> {
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writeln!(file, "impl<I: MemoryInterface> Core<I> {{")?;
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writeln!(
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@ -227,8 +240,7 @@ fn generate_thumb_lut(file: &mut fs::File) -> Result<(), std::io::Error> {
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)?;
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for i in 0..1024 {
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let thumb_fmt = thumb_decode(i << 6);
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let handler_name = thumb_format_to_handler(thumb_fmt);
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let (thumb_fmt, handler_name) = thumb_decode(i << 6);
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writeln!(
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file,
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" /* {:#x} */
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@ -254,16 +266,16 @@ fn generate_arm_lut(file: &mut fs::File) -> Result<(), std::io::Error> {
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" pub const ARM_LUT: [ArmInstructionInfo<I>; 4096] = ["
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)?;
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for i in 0..4096 {
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let handler_name = arm_decode(((i & 0xff0) << 16) | ((i & 0x00f) << 4));
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let (arm_fmt, handler_name) = arm_decode(((i & 0xff0) << 16) | ((i & 0x00f) << 4));
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writeln!(
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file,
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" /* {:#x} */
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ArmInstructionInfo {{
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handler_fn: Core::{},
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#[cfg(feature = \"debugger\")]
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fmt: ArmFormat::Undefined,
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fmt: ArmFormat::{},
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}} ,",
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i, handler_name
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i, handler_name, arm_fmt
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)?;
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}
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writeln!(file, " ];")?;
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@ -272,7 +272,7 @@ impl<I: MemoryInterface> Core<I> {
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1 => BarrelShiftOpCode::LSR,
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2 => BarrelShiftOpCode::ASR,
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3 => BarrelShiftOpCode::ROR,
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_ => unreachable!(),
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_ => unsafe { std::hint::unreachable_unchecked() },
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};
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if SHIFT_BY_REG {
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let rs = offset.bit_range(8..12) as usize;
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@ -10,19 +10,23 @@ use MemoryAccess::*;
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impl<I: MemoryInterface> Core<I> {
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/// Format 1
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/// Execution Time: 1S
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pub(in super::super) fn exec_thumb_move_shifted_reg(&mut self, insn: u16) -> CpuAction {
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pub(in super::super) fn exec_thumb_move_shifted_reg<const BS_OP: u8, const OFFSET5: u8>(
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&mut self,
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insn: u16,
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) -> CpuAction {
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let rd = (insn & 0b111) as usize;
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let rs = insn.bit_range(3..6) as usize;
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let shift_amount = insn.offset5() as u8 as u32;
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let shift_amount = OFFSET5 as u32;
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let mut carry = self.cpsr.C();
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let op2 = self.barrel_shift_op(
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insn.format1_op(),
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self.gpr[rs],
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shift_amount,
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&mut carry,
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true,
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);
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let bsop = match BS_OP {
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0 => BarrelShiftOpCode::LSL,
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1 => BarrelShiftOpCode::LSR,
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2 => BarrelShiftOpCode::ASR,
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3 => BarrelShiftOpCode::ROR,
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_ => unsafe { std::hint::unreachable_unchecked() },
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};
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let op2 = self.barrel_shift_op(bsop, self.gpr[rs], shift_amount, &mut carry, true);
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self.gpr[rd] = op2;
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self.alu_update_flags(op2, false, carry, self.cpsr.V());
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@ -31,18 +35,21 @@ impl<I: MemoryInterface> Core<I> {
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/// Format 2
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/// Execution Time: 1S
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pub(in super::super) fn exec_thumb_add_sub(&mut self, insn: u16) -> CpuAction {
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pub(in super::super) fn exec_thumb_add_sub<
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const SUB: bool,
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const IMM: bool,
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const RN: usize,
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>(
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&mut self,
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insn: u16,
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) -> CpuAction {
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let rd = (insn & 0b111) as usize;
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let op1 = self.get_reg(insn.rs());
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let op2 = if insn.is_immediate_operand() {
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insn.rn() as u32
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} else {
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self.get_reg(insn.rn())
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};
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let op2 = if IMM { RN as u32 } else { self.get_reg(RN) };
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let mut carry = self.cpsr.C();
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let mut overflow = self.cpsr.V();
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let result = if insn.is_subtract() {
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let result = if SUB {
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self.alu_sub_flags(op1, op2, &mut carry, &mut overflow)
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} else {
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self.alu_add_flags(op1, op2, &mut carry, &mut overflow)
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