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fix: bug in some ALU opcodes

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Former-commit-id: 7e05a11a709ad7f834916afa82ec5460068363f9
This commit is contained in:
Michel Heily 2019-07-06 18:47:42 +03:00
parent efb5d361d6
commit 8dc169d25d
1 changed files with 2 additions and 2 deletions
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4
src/arm7tdmi/arm/exec.rs
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@ -170,8 +170,8 @@ impl Core {
ArmOpCode::RSB => Self::alu_sub_update_carry(op2, op1, &mut carry), ArmOpCode::RSB => Self::alu_sub_update_carry(op2, op1, &mut carry),
ArmOpCode::ADD | ArmOpCode::CMN => Self::alu_add_update_carry(op1, op2, &mut carry), ArmOpCode::ADD | ArmOpCode::CMN => Self::alu_add_update_carry(op1, op2, &mut carry),
ArmOpCode::ADC => Self::alu_add_update_carry(op1, op2.wrapping_add(C), &mut carry), ArmOpCode::ADC => Self::alu_add_update_carry(op1, op2.wrapping_add(C), &mut carry),
ArmOpCode::SBC => Self::alu_add_update_carry(op1, op2.wrapping_sub(1 - C), &mut carry), ArmOpCode::SBC => Self::alu_sub_update_carry(op1, op2.wrapping_sub(1 - C), &mut carry),
ArmOpCode::RSC => Self::alu_add_update_carry(op2, op1.wrapping_sub(1 - C), &mut carry), ArmOpCode::RSC => Self::alu_sub_update_carry(op2, op1.wrapping_sub(1 - C), &mut carry),
ArmOpCode::ORR => op1 | op2, ArmOpCode::ORR => op1 | op2,
ArmOpCode::MOV => op2, ArmOpCode::MOV => op2,
ArmOpCode::BIC => op1 & (!op2), ArmOpCode::BIC => op1 & (!op2),