core: debugger: Fix traces

Former-commit-id: fbdaef86e2164ad1eeb5267041070958c024ceda
Former-commit-id: 643bcfe7ebccf77297d2371715490b3005e91d92
This commit is contained in:
Michel Heily 2021-06-09 01:33:12 +03:00
parent ff472db249
commit 97704f2621
4 changed files with 65 additions and 26 deletions

View file

@ -29,6 +29,14 @@ impl<I: MemoryInterface> Core<I> {
Irq => (CpuMode::Irq, true, false), Irq => (CpuMode::Irq, true, false),
Fiq => (CpuMode::Fiq, true, true), Fiq => (CpuMode::Fiq, true, true),
}; };
#[cfg(feature = "debugger")]
{
if self.dbg.trace_exceptions {
trace!("exception {:?} lr={:x} new_mode={:?}", e, lr, new_mode);
}
}
let new_bank = new_mode.bank_index(); let new_bank = new_mode.bank_index();
self.banks.spsr_bank[new_bank] = self.cpsr; self.banks.spsr_bank[new_bank] = self.cpsr;
self.banks.gpr_banked_r14[new_bank] = lr; self.banks.gpr_banked_r14[new_bank] = lr;

View file

@ -225,15 +225,7 @@ impl Debugger {
} }
TraceToggle(flags) => { TraceToggle(flags) => {
if flags.contains(TraceFlags::TRACE_OPCODE) { if flags.contains(TraceFlags::TRACE_OPCODE) {
gba.cpu.dbg.trace_opcodes = !gba.cpu.dbg.trace_opcodes; println!("[*] opcode tracing not implemented")
println!(
"[*] opcode tracing {}",
if gba.cpu.dbg.trace_opcodes {
"on"
} else {
"off"
}
)
} }
if flags.contains(TraceFlags::TRACE_EXCEPTIONS) { if flags.contains(TraceFlags::TRACE_EXCEPTIONS) {
gba.cpu.dbg.trace_exceptions = !gba.cpu.dbg.trace_exceptions; gba.cpu.dbg.trace_exceptions = !gba.cpu.dbg.trace_exceptions;
@ -247,10 +239,26 @@ impl Debugger {
) )
} }
if flags.contains(TraceFlags::TRACE_DMA) { if flags.contains(TraceFlags::TRACE_DMA) {
println!("[*] dma tracing not implemented"); gba.sysbus.io.dmac.trace = !gba.sysbus.io.dmac.trace;
println!(
"[*] dma tracing {}",
if gba.sysbus.io.dmac.trace {
"on"
} else {
"off"
}
)
} }
if flags.contains(TraceFlags::TRACE_TIMERS) { if flags.contains(TraceFlags::TRACE_TIMERS) {
gba.sysbus.io.timers.trace = !gba.sysbus.io.timers.trace; gba.sysbus.io.timers.trace = !gba.sysbus.io.timers.trace;
println!(
"[*] timer tracing {}",
if gba.sysbus.io.timers.trace {
"on"
} else {
"off"
}
)
} }
} }
SaveState(save_path) => { SaveState(save_path) => {

View file

@ -83,19 +83,24 @@ impl DmaChannel {
self.wc = value as u32; self.wc = value as u32;
} }
pub fn write_dma_ctrl(&mut self, value: u16) -> bool { pub fn write_dma_ctrl(&mut self, value: u16, #[cfg(feature = "debugger")] trace: bool) -> bool {
let ctrl = DmaChannelCtrl(value); let ctrl = DmaChannelCtrl(value);
let timing = ctrl.timing(); let timing = ctrl.timing();
let mut start_immediately = false; let mut start_immediately = false;
if ctrl.is_enabled() && !self.ctrl.is_enabled() { if ctrl.is_enabled() && !self.ctrl.is_enabled() {
// trace!( #[cfg(feature = "debugger")]
// "DMA{} enabled! timing={} src={:#x} dst={:#x} cnt={}", {
// self.id, if trace {
// timing, trace!(
// self.src, "DMA{} enabled! timing={} src={:#x} dst={:#x} cnt={}",
// self.dst, self.id,
// self.wc timing,
// ); self.src,
self.dst,
self.wc
);
}
}
self.running = true; self.running = true;
start_immediately = timing == 0; start_immediately = timing == 0;
self.internal.src_addr = self.src; self.internal.src_addr = self.src;
@ -195,6 +200,8 @@ pub struct DmaController {
#[serde(skip)] #[serde(skip)]
#[serde(default = "Scheduler::new_shared")] #[serde(default = "Scheduler::new_shared")]
scheduler: SharedScheduler, scheduler: SharedScheduler,
#[cfg(feature = "debugger")]
pub trace: bool,
} }
impl InterruptConnect for DmaController { impl InterruptConnect for DmaController {
@ -222,6 +229,9 @@ impl DmaController {
], ],
pending_set: 0, pending_set: 0,
scheduler: scheduler, scheduler: scheduler,
#[cfg(feature = "debugger")]
trace: false,
} }
} }
@ -246,7 +256,11 @@ impl DmaController {
6 => self.channels[channel_id].write_dst_high(value), 6 => self.channels[channel_id].write_dst_high(value),
8 => self.channels[channel_id].write_word_count(value), 8 => self.channels[channel_id].write_word_count(value),
10 => { 10 => {
if self.channels[channel_id].write_dma_ctrl(value) { #[cfg(feature = "debugger")]
let start_immediately = self.channels[channel_id].write_dma_ctrl(value, self.trace);
#[cfg(not(feature = "debugger"))]
let start_immediately = self.channels[channel_id].write_dma_ctrl(value);
if start_immediately {
// DMA actually starts after 3 cycles // DMA actually starts after 3 cycles
self.scheduler self.scheduler
.push(EventType::DmaActivateChannel(channel_id), 3); .push(EventType::DmaActivateChannel(channel_id), 3);

View file

@ -98,6 +98,8 @@ pub struct Timers {
scheduler: SharedScheduler, scheduler: SharedScheduler,
timers: [Timer; 4], timers: [Timer; 4],
running_timers: u8, running_timers: u8,
#[cfg(feature = "debugger")]
pub trace: bool, pub trace: bool,
} }
@ -139,6 +141,8 @@ impl Timers {
Timer::new(3, interrupt_flags.clone()), Timer::new(3, interrupt_flags.clone()),
], ],
running_timers: 0, running_timers: 0,
#[cfg(feature = "debugger")]
trace: false, trace: false,
} }
} }
@ -199,6 +203,7 @@ impl Timers {
pub fn write_timer_ctl(&mut self, id: usize, value: u16) { pub fn write_timer_ctl(&mut self, id: usize, value: u16) {
let timer = &mut self.timers[id]; let timer = &mut self.timers[id];
let new_ctl = TimerCtl(value); let new_ctl = TimerCtl(value);
#[cfg(feature = "debugger")]
let old_enabled = timer.ctl.enabled(); let old_enabled = timer.ctl.enabled();
let new_enabled = new_ctl.enabled(); let new_enabled = new_ctl.enabled();
let cascade = new_ctl.cascade(); let cascade = new_ctl.cascade();
@ -212,12 +217,16 @@ impl Timers {
self.running_timers &= !(1 << id); self.running_timers &= !(1 << id);
self.cancel_timer_event(id); self.cancel_timer_event(id);
} }
if old_enabled != new_enabled {
trace!( #[cfg(feature = "debugger")]
"TMR{} {}", {
id, if self.trace && old_enabled != new_enabled {
if new_enabled { "enabled" } else { "disabled" } trace!(
); "TMR{} {}",
id,
if new_enabled { "enabled" } else { "disabled" }
);
}
} }
} }