core: debugger: Fix traces

Former-commit-id: fbdaef86e2164ad1eeb5267041070958c024ceda
Former-commit-id: 643bcfe7ebccf77297d2371715490b3005e91d92

core/src/arm7tdmi/exception.rs

@@ -29,6 +29,14 @@ impl<I: MemoryInterface> Core<I> {
             Irq => (CpuMode::Irq, true, false),
             Fiq => (CpuMode::Fiq, true, true),
         };
+
+        #[cfg(feature = "debugger")]
+        {
+            if self.dbg.trace_exceptions {
+                trace!("exception {:?} lr={:x} new_mode={:?}", e, lr, new_mode);
+            }
+        }
+
         let new_bank = new_mode.bank_index();
         self.banks.spsr_bank[new_bank] = self.cpsr;
         self.banks.gpr_banked_r14[new_bank] = lr;

core/src/debugger/command.rs

@@ -225,15 +225,7 @@ impl Debugger {
             }
             TraceToggle(flags) => {
                 if flags.contains(TraceFlags::TRACE_OPCODE) {
-                    gba.cpu.dbg.trace_opcodes = !gba.cpu.dbg.trace_opcodes;
-                    println!(
-                        "[*] opcode tracing {}",
-                        if gba.cpu.dbg.trace_opcodes {
-                            "on"
-                        } else {
-                            "off"
-                        }
-                    )
+                    println!("[*] opcode tracing not implemented")
                 }
                 if flags.contains(TraceFlags::TRACE_EXCEPTIONS) {
                     gba.cpu.dbg.trace_exceptions = !gba.cpu.dbg.trace_exceptions;
@@ -247,10 +239,26 @@ impl Debugger {
                     )
                 }
                 if flags.contains(TraceFlags::TRACE_DMA) {
-                    println!("[*] dma tracing not implemented");
+                    gba.sysbus.io.dmac.trace = !gba.sysbus.io.dmac.trace;
+                    println!(
+                        "[*] dma tracing {}",
+                        if gba.sysbus.io.dmac.trace {
+                            "on"
+                        } else {
+                            "off"
+                        }
+                    )
                 }
                 if flags.contains(TraceFlags::TRACE_TIMERS) {
                     gba.sysbus.io.timers.trace = !gba.sysbus.io.timers.trace;
+                    println!(
+                        "[*] timer tracing {}",
+                        if gba.sysbus.io.timers.trace {
+                            "on"
+                        } else {
+                            "off"
+                        }
+                    )
                 }
             }
             SaveState(save_path) => {

core/src/dma.rs

@@ -83,19 +83,24 @@ impl DmaChannel {
         self.wc = value as u32;
     }
 
-    pub fn write_dma_ctrl(&mut self, value: u16) -> bool {
+    pub fn write_dma_ctrl(&mut self, value: u16, #[cfg(feature = "debugger")] trace: bool) -> bool {
         let ctrl = DmaChannelCtrl(value);
         let timing = ctrl.timing();
         let mut start_immediately = false;
         if ctrl.is_enabled() && !self.ctrl.is_enabled() {
-            // trace!(
-            //     "DMA{} enabled! timing={} src={:#x} dst={:#x} cnt={}",
-            //     self.id,
-            //     timing,
-            //     self.src,
-            //     self.dst,
-            //     self.wc
-            // );
+            #[cfg(feature = "debugger")]
+            {
+                if trace {
+                    trace!(
+                        "DMA{} enabled! timing={} src={:#x} dst={:#x} cnt={}",
+                        self.id,
+                        timing,
+                        self.src,
+                        self.dst,
+                        self.wc
+                    );
+                }
+            }
             self.running = true;
             start_immediately = timing == 0;
             self.internal.src_addr = self.src;
@@ -195,6 +200,8 @@ pub struct DmaController {
     #[serde(skip)]
     #[serde(default = "Scheduler::new_shared")]
     scheduler: SharedScheduler,
+    #[cfg(feature = "debugger")]
+    pub trace: bool,
 }
 
 impl InterruptConnect for DmaController {
@@ -222,6 +229,9 @@ impl DmaController {
             ],
             pending_set: 0,
             scheduler: scheduler,
+
+            #[cfg(feature = "debugger")]
+            trace: false,
         }
     }
 
@@ -246,7 +256,11 @@ impl DmaController {
             6 => self.channels[channel_id].write_dst_high(value),
             8 => self.channels[channel_id].write_word_count(value),
             10 => {
-                if self.channels[channel_id].write_dma_ctrl(value) {
+                #[cfg(feature = "debugger")]
+                let start_immediately = self.channels[channel_id].write_dma_ctrl(value, self.trace);
+                #[cfg(not(feature = "debugger"))]
+                let start_immediately = self.channels[channel_id].write_dma_ctrl(value);
+                if start_immediately {
                     // DMA actually starts after 3 cycles
                     self.scheduler
                         .push(EventType::DmaActivateChannel(channel_id), 3);

core/src/timer.rs

@@ -98,6 +98,8 @@ pub struct Timers {
     scheduler: SharedScheduler,
     timers: [Timer; 4],
     running_timers: u8,
+
+    #[cfg(feature = "debugger")]
     pub trace: bool,
 }
 
@@ -139,6 +141,8 @@ impl Timers {
                 Timer::new(3, interrupt_flags.clone()),
             ],
             running_timers: 0,
+
+            #[cfg(feature = "debugger")]
             trace: false,
         }
     }
@@ -199,6 +203,7 @@ impl Timers {
     pub fn write_timer_ctl(&mut self, id: usize, value: u16) {
         let timer = &mut self.timers[id];
         let new_ctl = TimerCtl(value);
+        #[cfg(feature = "debugger")]
         let old_enabled = timer.ctl.enabled();
         let new_enabled = new_ctl.enabled();
         let cascade = new_ctl.cascade();
@@ -212,7 +217,10 @@ impl Timers {
             self.running_timers &= !(1 << id);
             self.cancel_timer_event(id);
         }
-        if old_enabled != new_enabled {
+
+        #[cfg(feature = "debugger")]
+        {
+            if self.trace && old_enabled != new_enabled {
                 trace!(
                     "TMR{} {}",
                     id,
@@ -220,6 +228,7 @@ impl Timers {
                 );
             }
         }
+    }
 
     #[inline]
     fn read_timer_data(&mut self, id: usize) -> u16 {