diff --git a/src/core/arm7tdmi/cpu.rs b/src/core/arm7tdmi/cpu.rs
index 111284b..b5b36b1 100644
--- a/src/core/arm7tdmi/cpu.rs
+++ b/src/core/arm7tdmi/cpu.rs
@@ -106,12 +106,14 @@ impl Core {
     pub fn set_reg(&mut self, r: usize, val: u32) {
         match r {
             0...14 => self.gpr[r] = val,
-            15 => self.pc = {
-                match self.cpsr.state() {
-                    CpuState::THUMB => val & !1,
-                    CpuState::ARM => val & !3
+            15 => {
+                self.pc = {
+                    match self.cpsr.state() {
+                        CpuState::THUMB => val & !1,
+                        CpuState::ARM => val & !3,
+                    }
                 }
-            },
+            }
             _ => panic!("invalid register"),
         }
     }
diff --git a/src/core/arm7tdmi/thumb/exec.rs b/src/core/arm7tdmi/thumb/exec.rs
index b611557..e9b43ba 100644
--- a/src/core/arm7tdmi/thumb/exec.rs
+++ b/src/core/arm7tdmi/thumb/exec.rs
@@ -231,7 +231,7 @@ impl Core {
         sb: &mut SysBus,
         insn: ThumbInstruction,
         addr: Addr,
-        is_transferring_bytes: bool
+        is_transferring_bytes: bool,
     ) -> CpuExecResult {
         let rd = (insn.raw & 0b111) as usize;
         if insn.is_load() {