feat(eeprom): Cleanup eeprom code. still not working
Former-commit-id: 5cc2b897796a35d3b3bc6c346cf275826e9f4b7c
This commit is contained in:
Michel Heily
parent
1f073199b3
commit
990ce40e35
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@ -1,4 +1,4 @@
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use super::{BackupMemoryInterface};
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use super::BackupMemoryInterface;
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use num::FromPrimitive;
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use serde::{Deserialize, Serialize};
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@ -31,9 +31,9 @@ enum SpiState {
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RxInstruction,
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RxAddress(SpiInstruction),
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StopBit(SpiInstruction),
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TxDummy(SpiInstruction),
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TxData(usize),
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RxData(usize),
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TxDummy,
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TxData,
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RxData,
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}
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impl Default for SpiState {
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@ -54,7 +54,7 @@ where
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rx_buffer: u64,
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tx_count: usize,
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tx_buffer: u8,
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tx_buffer: u64,
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address: usize,
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}
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@ -78,22 +78,6 @@ where
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}
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}
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fn rx(&mut self, bit: u8) {
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// data is receieved MSB first
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let bit = bit & 1;
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self.rx_buffer = (self.rx_buffer << 1) | (if bit & 1 != 0 { 1 } else { 0 });
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self.rx_count += 1;
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}
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fn tx(&mut self) -> u8 {
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// data is transmitted MSB first
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let bit = self.tx_buffer >> 7;
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self.tx_buffer = self.tx_buffer << 1;
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self.tx_count += 1;
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bit
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}
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fn reset_rx_buffer(&mut self) {
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self.rx_buffer = 0;
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self.rx_count = 0;
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@ -104,12 +88,26 @@ where
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self.tx_count = 0;
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}
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fn fill_tx_buffer(&mut self) {
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let mut tx_buffer = 0u64;
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for i in 0..8 {
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tx_buffer = tx_buffer << 8;
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tx_buffer |= self.memory.read(self.address + i) as u64;
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}
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self.tx_buffer = tx_buffer;
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self.tx_count = 0;
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}
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fn clock_data_in(&mut self, si: u8) {
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use SpiInstruction::*;
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use SpiState::*;
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// Read the si signal into the rx_buffer
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self.rx(si);
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trace!("({:?}) RX bit {}", self.state, si);
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self.rx_buffer = (self.rx_buffer << 1) | (if si & 1 != 0 { 1 } else { 0 });
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self.rx_count += 1;
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let mut next_state: Option<SpiState> = None;
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match self.state {
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RxInstruction => {
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@ -119,96 +117,97 @@ where
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"invalid spi command {:#010b}",
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self.rx_buffer as u8
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));
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self.state = RxAddress(insn);
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next_state = Some(RxAddress(insn));
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self.reset_rx_buffer();
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}
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}
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RxAddress(insn) => {
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if self.rx_count == 6 {
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self.address = (self.rx_buffer as usize) * 8;
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self.state = match insn {
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Read => StopBit(insn),
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Write => RxData(0),
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};
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debug!("recvd address = {:#x}", self.address);
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match insn {
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Read => {
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self.reset_rx_buffer();
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self.reset_tx_buffer();
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next_state = Some(StopBit(insn));
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}
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Write => {
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next_state = Some(RxData);
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self.reset_rx_buffer();
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}
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}
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}
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}
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StopBit(Read) => {
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if si != 0 {
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panic!(
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"SPI Read - bit 0 was expected for command termination (debug={:?})",
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*self
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);
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}
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self.state = TxDummy(Read);
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next_state = Some(TxDummy);
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self.reset_rx_buffer();
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self.reset_tx_buffer();
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}
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RxData(rx_bytes) => {
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if rx_bytes < 8 {
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if self.rx_count % 8 == 0 {
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if rx_bytes + 1 == 8 {
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self.state = StopBit(Write);
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self.reset_rx_buffer();
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} else {
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let byte = (self.rx_buffer & 0xff) as u8;
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self.memory.write(self.address, byte);
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self.reset_rx_buffer();
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self.address += 1;
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self.state = RxData(rx_bytes + 1);
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}
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RxData => {
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if self.rx_count == 64 {
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let mut data = self.rx_buffer;
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debug!("writing {:x} to memory", data);
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for i in 0..8 {
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self.memory
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.write(self.address + (7 - i), (data & 0xff) as u8);
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data = data >> 8;
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}
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next_state = Some(StopBit(Write));
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self.reset_rx_buffer();
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}
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}
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StopBit(Write) => {
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if si != 0 {
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panic!(
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"SPI Write - bit 0 was expected for command termination (debug={:?})",
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*self
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);
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}
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self.state = RxInstruction;
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self.reset_rx_buffer();
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self.reset_tx_buffer();
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}
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_ => {}
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}
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if let Some(next_state) = next_state {
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self.state = next_state;
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}
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}
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fn clock_data_out(&mut self) -> u8 {
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use SpiState::*;
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match self.state {
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TxDummy(insn) => {
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let bit = self.tx();
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let mut next_state = None;
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let result = match self.state {
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TxDummy => {
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self.tx_count += 1;
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if self.tx_count == 4 {
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self.state = TxData(0);
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self.reset_tx_buffer();
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next_state = Some(TxData);
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self.fill_tx_buffer();
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debug!("transmitting data bits, tx_buffer = {:#x}", self.tx_buffer);
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}
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bit
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}
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TxData(tx_bytes) => {
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if tx_bytes < 8 {
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if self.tx_count % 8 == 0 {
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let byte = self.memory.read(self.address);
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self.tx_buffer = byte;
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self.address += 1;
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self.state = TxData(tx_bytes + 1);
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}
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self.tx()
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} else {
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self.state = RxInstruction;
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self.reset_rx_buffer();
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self.reset_tx_buffer();
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0
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}
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TxData => {
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self.tx_count += 1;
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if self.tx_count == 64 {
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self.reset_rx_buffer();
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self.reset_tx_buffer();
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next_state = Some(RxInstruction);
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0
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} else {
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let result = ((self.tx_buffer >> 63) & 1) as u8;
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self.tx_buffer = self.tx_buffer << 1;
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result
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}
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_ => self.tx(),
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}
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_ => 0,
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};
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trace!("({:?}) TX bit {}", self.state, result);
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if let Some(next_state) = next_state {
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self.state = next_state;
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}
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result
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}
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fn data_available(&self) -> bool {
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if let SpiState::TxData(_) = self.state {
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if let SpiState::TxData = self.state {
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true
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} else {
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false
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