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Return to rust stable, get rid of nightly features for now

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Former-commit-id: 1550bc0f70218c8a012f0631502eabbdf835d0ab
This commit is contained in:
Michel Heily 2020-02-14 14:33:22 +02:00
parent 11fb9d7eda
commit aeab3a82a3
3 changed files with 6 additions and 8 deletions
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4
src/core/cartridge/backup/eeprom.rs
View file

@ -335,7 +335,7 @@ impl EepromController {
if self.detect { if self.detect {
match (src, dst) { match (src, dst) {
// DMA to EEPROM // DMA to EEPROM
(_, 0x0d000000..0x0dffffff) => { (_, 0x0d000000..=0x0dffffff) => {
debug!("caught eeprom dma transfer src={:#x} dst={:#x} count={}", src, dst, count); debug!("caught eeprom dma transfer src={:#x} dst={:#x} count={}", src, dst, count);
let eeprom_type = match count { let eeprom_type = match count {
// Read(11) + 6bit address + stop bit // Read(11) + 6bit address + stop bit
@ -353,7 +353,7 @@ impl EepromController {
self.detect = false; self.detect = false;
} }
// EEPROM to DMA // EEPROM to DMA
(0x0d000000..0x0dffffff, _) => { (0x0d000000..=0x0dffffff, _) => {
panic!("reading from eeprom when real size is not detected yet is not supported by this emulator") panic!("reading from eeprom when real size is not detected yet is not supported by this emulator")
} }
_ => {/* Not a eeprom dma, doing nothing */} _ => {/* Not a eeprom dma, doing nothing */}

6
src/core/iodev.rs
View file

@ -81,7 +81,7 @@ impl Bus for IoDevices {
REG_TM0CNT_L..=REG_TM3CNT_H => io.timers.handle_read(io_addr), REG_TM0CNT_L..=REG_TM3CNT_H => io.timers.handle_read(io_addr),
REG_SOUND1CNT_L..DMA_BASE => io.sound.handle_read(io_addr), SOUND_BASE..=SOUND_END => io.sound.handle_read(io_addr),
REG_DMA0CNT_H => io.dmac.channels[0].ctrl.0, REG_DMA0CNT_H => io.dmac.channels[0].ctrl.0,
REG_DMA1CNT_H => io.dmac.channels[1].ctrl.0, REG_DMA1CNT_H => io.dmac.channels[1].ctrl.0,
REG_DMA2CNT_H => io.dmac.channels[2].ctrl.0, REG_DMA2CNT_H => io.dmac.channels[2].ctrl.0,
@ -221,7 +221,7 @@ impl Bus for IoDevices {
REG_TM0CNT_L..=REG_TM3CNT_H => io.timers.handle_write(io_addr, value), REG_TM0CNT_L..=REG_TM3CNT_H => io.timers.handle_write(io_addr, value),
REG_SOUND1CNT_L..DMA_BASE => { SOUND_BASE..=SOUND_END => {
io.sound.handle_write(io_addr, value); io.sound.handle_write(io_addr, value);
} }
@ -329,6 +329,7 @@ pub mod consts {
pub const REG_BLDCNT: Addr = 0x0400_0050; // 2 R/W Color Special Effects Selection pub const REG_BLDCNT: Addr = 0x0400_0050; // 2 R/W Color Special Effects Selection
pub const REG_BLDALPHA: Addr = 0x0400_0052; // 2 R/W Alpha Blending Coefficients pub const REG_BLDALPHA: Addr = 0x0400_0052; // 2 R/W Alpha Blending Coefficients
pub const REG_BLDY: Addr = 0x0400_0054; // 2 W Brightness (Fade-In/Out) Coefficient pub const REG_BLDY: Addr = 0x0400_0054; // 2 W Brightness (Fade-In/Out) Coefficient
pub const SOUND_BASE: Addr = REG_SOUND1CNT_L;
pub const REG_SOUND1CNT_L: Addr = 0x0400_0060; // 2 R/W Channel 1 Sweep register (NR10) pub const REG_SOUND1CNT_L: Addr = 0x0400_0060; // 2 R/W Channel 1 Sweep register (NR10)
pub const REG_SOUND1CNT_H: Addr = 0x0400_0062; // 2 R/W Channel 1 Duty/Length/Envelope (NR11, NR12) pub const REG_SOUND1CNT_H: Addr = 0x0400_0062; // 2 R/W Channel 1 Duty/Length/Envelope (NR11, NR12)
pub const REG_SOUND1CNT_X: Addr = 0x0400_0064; // 2 R/W Channel 1 Frequency/Control (NR13, NR14) pub const REG_SOUND1CNT_X: Addr = 0x0400_0064; // 2 R/W Channel 1 Frequency/Control (NR13, NR14)
@ -346,6 +347,7 @@ pub mod consts {
pub const REG_WAVE_RAM: Addr = 0x0400_0090; // Channel 3 Wave Pattern RAM (2 banks!!) pub const REG_WAVE_RAM: Addr = 0x0400_0090; // Channel 3 Wave Pattern RAM (2 banks!!)
pub const REG_FIFO_A: Addr = 0x0400_00A0; // 4 W Channel A FIFO, Data 0-3 pub const REG_FIFO_A: Addr = 0x0400_00A0; // 4 W Channel A FIFO, Data 0-3
pub const REG_FIFO_B: Addr = 0x0400_00A4; // 4 W Channel B FIFO, Data 0-3 pub const REG_FIFO_B: Addr = 0x0400_00A4; // 4 W Channel B FIFO, Data 0-3
pub const SOUND_END: Addr = REG_FIFO_B+4;
pub const DMA_BASE: Addr = REG_DMA0SAD; pub const DMA_BASE: Addr = REG_DMA0SAD;
pub const REG_DMA0SAD: Addr = 0x0400_00B0; // 4 W DMA 0 Source Address pub const REG_DMA0SAD: Addr = 0x0400_00B0; // 4 W DMA 0 Source Address
pub const REG_DMA0DAD: Addr = 0x0400_00B4; // 4 W DMA 0 Destination Address pub const REG_DMA0DAD: Addr = 0x0400_00B4; // 4 W DMA 0 Destination Address

4
src/lib.rs
View file

@ -1,7 +1,3 @@
#![feature(asm)]
#![feature(core_intrinsics)]
#![feature(exclusive_range_pattern)]
#[macro_use] #[macro_use]
extern crate serde; extern crate serde;