gpu: Refactor Gpu::current_scanline -> Gpu::vcount

Former-commit-id: fe17235bd7e953195e6348e4670bf0520a78270a
This commit is contained in:
Michel Heily 2019-12-28 20:25:27 +02:00
parent cc4f328691
commit b13c3026c8
5 changed files with 17 additions and 17 deletions

View file

@ -206,7 +206,7 @@ pub struct Gpu {
cycles: usize,
// registers
pub current_scanline: usize, // VCOUNT
pub vcount: usize, // VCOUNT
pub dispcnt: DisplayControl,
pub dispstat: DisplayStatus,
@ -245,7 +245,7 @@ impl Gpu {
bldy: 0,
state: HDraw,
current_scanline: 0,
vcount: 0,
cycles: 0,
obj_line: Scanline::default(),
obj_line_priorities: Scanline([3; DISPLAY_WIDTH]),
@ -304,7 +304,7 @@ impl Gpu {
let (bg_width, bg_height) = self.bg[bg].bgcnt.size_regular();
let screen_y = self.current_scanline as u32;
let screen_y = self.vcount as u32;
let mut screen_x = 0;
// calculate the bg coords at the top-left corner, including wraparound
@ -375,7 +375,7 @@ impl Gpu {
}
fn scanline_mode3(&mut self, bg: usize, sb: &mut SysBus) {
let y = self.current_scanline;
let y = self.vcount;
for x in 0..DISPLAY_WIDTH {
let pixel_index = index2d!(u32, x, y, DISPLAY_WIDTH);
@ -392,7 +392,7 @@ impl Gpu {
_ => unreachable!(),
};
let y = self.current_scanline;
let y = self.vcount;
for x in 0..DISPLAY_WIDTH {
let bitmap_index = index2d!(x, y, DISPLAY_WIDTH);
@ -446,7 +446,7 @@ impl Gpu {
self.mosaic_sfx();
let post_sfx_line = self.composite_sfx(sb);
for x in 0..DISPLAY_WIDTH {
self.frame_buffer.0[x + self.current_scanline * DISPLAY_WIDTH] =
self.frame_buffer.0[x + self.vcount * DISPLAY_WIDTH] =
post_sfx_line[x].to_rgb24();
}
}
@ -456,10 +456,10 @@ impl Gpu {
}
fn update_vcount(&mut self, value: usize, irqs: &mut IrqBitmask) {
self.current_scanline = value;
self.vcount = value;
let vcount_setting = self.dispstat.vcount_setting();
self.dispstat
.set_vcount_flag(vcount_setting == self.current_scanline as u16);
.set_vcount_flag(vcount_setting == self.vcount as u16);
if self.dispstat.vcount_irq_enable() && self.dispstat.get_vcount_flag() {
irqs.set_LCD_VCounterMatch(true);
@ -488,9 +488,9 @@ impl Gpu {
self.cycles -= CYCLES_HBLANK;
self.dispstat.set_hblank_flag(false);
self.update_vcount(self.current_scanline + 1, irqs);
self.update_vcount(self.vcount + 1, irqs);
if self.current_scanline < DISPLAY_HEIGHT {
if self.vcount < DISPLAY_HEIGHT {
self.render_scanline(sb);
self.state = HDraw;
} else {
@ -507,8 +507,8 @@ impl Gpu {
if self.cycles > CYCLES_SCANLINE {
self.cycles -= CYCLES_SCANLINE;
if self.current_scanline < DISPLAY_HEIGHT + VBLANK_LINES - 1 {
self.update_vcount(self.current_scanline + 1, irqs);
if self.vcount < DISPLAY_HEIGHT + VBLANK_LINES - 1 {
self.update_vcount(self.vcount + 1, irqs);
} else {
self.update_vcount(0, irqs);
self.dispstat.set_vblank_flag(false);

View file

@ -14,7 +14,7 @@ impl Gpu {
for bg in 0..4 {
if self.dispcnt.disp_bg(bg) && self.bg[bg].bgcnt.mosaic() {
let y = self.current_scanline as usize;
let y = self.vcount as usize;
if y % vsize == 0 {
self.bg[bg].mosaic_first_row = self.bg[bg].line.clone();
}

View file

@ -96,7 +96,7 @@ impl Gpu {
}
fn render_affine_obj(&mut self, sb: &SysBus, obj: ObjAttrs, _obj_num: usize) {
let screen_y = self.current_scanline as i32;
let screen_y = self.vcount as i32;
let (ref_x, ref_y) = obj.coords();
@ -177,7 +177,7 @@ impl Gpu {
}
fn render_normal_obj(&mut self, sb: &SysBus, obj: ObjAttrs, _obj_num: usize) {
let screen_y = self.current_scanline as i32;
let screen_y = self.vcount as i32;
let (ref_x, ref_y) = obj.coords();
let (obj_w, obj_h) = obj.size();

View file

@ -149,7 +149,7 @@ impl Gpu {
pub fn composite_sfx(&self, sb: &SysBus) -> Scanline<Rgb15> {
let mut line: Scanline<Rgb15> = Scanline::default();
let y = self.current_scanline;
let y = self.vcount;
for x in 0..DISPLAY_WIDTH {
let window = self.get_active_window_type(x, y);
let wflags = self.get_window_flags(window);

View file

@ -62,7 +62,7 @@ impl Bus for IoDevices {
match io_addr {
REG_DISPCNT => io.gpu.dispcnt.0,
REG_DISPSTAT => io.gpu.dispstat.0,
REG_VCOUNT => io.gpu.current_scanline as u16,
REG_VCOUNT => io.gpu.vcount as u16,
REG_BG0CNT => io.gpu.bg[0].bgcnt.0,
REG_BG1CNT => io.gpu.bg[1].bgcnt.0,
REG_BG2CNT => io.gpu.bg[2].bgcnt.0,