From ba9b4662d43ea07e6a5b21c07c0904395bae11ff Mon Sep 17 00:00:00 2001
From: Michel Heily <michelheily@gmail.com>
Date: Sat, 31 Aug 2019 14:10:05 +0200
Subject: [PATCH] Fix SBC and RSC instructions

Needed to add 1-C and not substract 1-C


Former-commit-id: 339201a2cd41d777d3b3204995e698182032c80d
---
 src/core/arm7tdmi/alu.rs | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/core/arm7tdmi/alu.rs b/src/core/arm7tdmi/alu.rs
index 1276e55..14e3d42 100644
--- a/src/core/arm7tdmi/alu.rs
+++ b/src/core/arm7tdmi/alu.rs
@@ -324,8 +324,8 @@ impl Core {
             RSB => Self::alu_sub_flags(op2, op1, &mut carry, &mut overflow),
             ADD | CMN => Self::alu_add_flags(op1, op2, &mut carry, &mut overflow),
             ADC => Self::alu_add_flags(op1, op2.wrapping_add(C), &mut carry, &mut overflow),
-            SBC => Self::alu_sub_flags(op1, op2, &mut carry, &mut overflow).wrapping_sub(1 - C),
-            RSC => Self::alu_sub_flags(op2, op1, &mut carry, &mut overflow).wrapping_sub(1 - C),
+            SBC => Self::alu_sub_flags(op1, op2.wrapping_add(1 - C), &mut carry, &mut overflow),
+            RSC => Self::alu_sub_flags(op2, op1.wrapping_add(1 - C), &mut carry, &mut overflow),
             ORR => op1 | op2,
             MOV => op2,
             BIC => op1 & (!op2),
@@ -334,9 +334,11 @@ impl Core {
 
         self.cpsr.set_N(result < 0);
         self.cpsr.set_Z(result == 0);
-        self.cpsr.set_C(carry);
         if opcode.is_arithmetic() {
+            self.cpsr.set_C(carry);
             self.cpsr.set_V(overflow);
+        } else {
+            self.cpsr.set_C(self.bs_carry_out)
         }
 
         if opcode.is_setting_flags() {