arm: Add tests for ldr/str
And also test disassembling while at it..
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7898bf61f3
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bd7fd472cf
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@ -220,7 +220,7 @@ impl ArmInstruction {
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fn fmt_ldr_str(&self, f: &mut fmt::Formatter) -> fmt::Result {
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write!(
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f,
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"{mnem}{B}{cond}{T}\t{Rd}, ",
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"{mnem}{B}{T}{cond}\t{Rd}, ",
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mnem = if self.load_flag() { "ldr" } else { "str" },
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B = if self.transfer_size() == 1 { "b" } else { "" },
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cond = self.cond,
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@ -358,7 +358,7 @@ impl ArmInstruction {
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fn fmt_swi(&self, f: &mut fmt::Formatter) -> fmt::Result {
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write!(
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f,
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"swi{cond}\t#0x{comm:08x}",
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"swi{cond}\t#{comm:#x}",
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cond = self.cond,
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comm = self.swi_comment()
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)
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@ -2,7 +2,8 @@ use crate::bit::BitIndex;
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use crate::arm7tdmi;
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use arm7tdmi::cpu::{
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Core, CpuError, CpuExecResult, CpuInstruction, CpuPipelineAction, CpuResult, CpuState, Exception
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Core, CpuError, CpuExecResult, CpuInstruction, CpuPipelineAction, CpuResult, CpuState,
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Exception,
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};
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use super::super::sysbus::SysBus;
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@ -430,9 +430,8 @@ impl ArmInstruction {
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}
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}
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#[cfg(test)]
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/// All instructions constants were generated using an ARM assembler.
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mod tests {
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use super::*;
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@ -442,6 +441,7 @@ mod tests {
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let decoded = ArmInstruction::try_from(0xef001337).unwrap();
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assert_eq!(decoded.fmt, ArmInstructionFormat::SWI);
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assert_eq!(decoded.swi_comment(), 0x1337);
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assert_eq!(format!("{}", decoded), "swi\t#0x1337");
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}
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#[test]
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@ -450,7 +450,11 @@ mod tests {
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let decoded = ArmInstruction::try_from((0xea_00_00_02, 0x20)).unwrap();
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assert_eq!(decoded.fmt, ArmInstructionFormat::B_BL);
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assert_eq!(decoded.link_flag(), false);
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assert_eq!((decoded.pc as i32).wrapping_add(decoded.branch_offset()), 0x30);
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assert_eq!(
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(decoded.pc as i32).wrapping_add(decoded.branch_offset()),
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0x30
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);
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assert_eq!(format!("{}", decoded), "b\t0x30");
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}
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#[test]
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@ -459,6 +463,56 @@ mod tests {
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let decoded = ArmInstruction::try_from((0xeb_ff_ff_fa, 0x20)).unwrap();
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assert_eq!(decoded.fmt, ArmInstructionFormat::B_BL);
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assert_eq!(decoded.link_flag(), true);
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assert_eq!((decoded.pc as i32).wrapping_add(decoded.branch_offset()), 0x10);
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assert_eq!(
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(decoded.pc as i32).wrapping_add(decoded.branch_offset()),
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0x10
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);
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assert_eq!(format!("{}", decoded), "b\t0x10");
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}
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#[test]
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fn test_decode_ldr_preindex() {
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// ldreq r2, [r5, -r6, lsl #5]
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let decoded = ArmInstruction::try_from(0x07_15_22_86).unwrap();
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assert_eq!(decoded.fmt, ArmInstructionFormat::LDR_STR);
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assert_eq!(decoded.cond, ArmCond::Equal);
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assert_eq!(decoded.load_flag(), true);
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assert_eq!(decoded.pre_index_flag(), true);
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assert_eq!(decoded.write_back_flag(), false);
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assert_eq!(decoded.rd(), 2);
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assert_eq!(decoded.rn(), 5);
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assert_eq!(
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decoded.ldr_str_offset(),
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Ok(ArmShiftedValue::ShiftedRegister {
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reg: 6,
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shift: ArmRegisterShift::ShiftAmount(5, ArmShiftType::LSL),
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added: Some(false)
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})
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);
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assert_eq!(format!("{}", decoded), "ldreq\tr2, [r5, -r6, lsl #5]");
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}
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#[test]
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fn test_decode_str_postindex() {
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// strteq r2, [r4], -r7, lsl #8
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let decoded = ArmInstruction::try_from(0x06_24_24_47).unwrap();
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assert_eq!(decoded.fmt, ArmInstructionFormat::LDR_STR);
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assert_eq!(decoded.cond, ArmCond::Equal);
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assert_eq!(decoded.load_flag(), false);
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assert_eq!(decoded.pre_index_flag(), false);
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assert_eq!(decoded.write_back_flag(), true);
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assert_eq!(decoded.rd(), 2);
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assert_eq!(decoded.rn(), 4);
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assert_eq!(
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decoded.ldr_str_offset(),
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Ok(ArmShiftedValue::ShiftedRegister {
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reg: 7,
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shift: ArmRegisterShift::ShiftAmount(8, ArmShiftType::ASR),
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added: Some(false)
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})
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);
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assert_eq!(format!("{}", decoded), "strteq\tr2, [r4], -r7, asr #8");
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}
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}
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