Move cycle counting to CPU Core
This isn't accurate, I'm probably missing something but at least it'll make the instruction implementation more clean for now.. Former-commit-id: de24b15e1a51e1998207e5ea96fc8543f2553a26
This commit is contained in:
Michel Heily
parent
f8ebe26e5e
commit
be9499c76d
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@ -6,30 +6,22 @@ use crate::arm7tdmi::exception::Exception;
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use crate::arm7tdmi::psr::RegPSR;
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use crate::arm7tdmi::{Addr, CpuError, CpuResult, CpuState, DecodedInstruction, REG_PC};
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use crate::sysbus::SysBus;
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use super::{
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ArmFormat, ArmInstruction, ArmOpCode, ArmRegisterShift, ArmShiftType, ArmShiftedValue,
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};
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impl Core {
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pub fn exec_arm(&mut self, sysbus: &mut Bus, insn: ArmInstruction) -> CpuExecResult {
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pub fn exec_arm(&mut self, bus: &mut Bus, insn: ArmInstruction) -> CpuExecResult {
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if !self.check_arm_cond(insn.cond) {
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self.add_cycles(
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insn.pc + (self.word_size() as u32),
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sysbus,
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Seq + MemoryAccess32,
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);
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self.add_cycle();
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return Ok(CpuPipelineAction::IncPC);
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}
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match insn.fmt {
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ArmFormat::BX => self.exec_bx(sysbus, insn),
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ArmFormat::B_BL => self.exec_b_bl(sysbus, insn),
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ArmFormat::DP => self.exec_data_processing(sysbus, insn),
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ArmFormat::SWI => self.exec_swi(sysbus, insn),
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ArmFormat::LDR_STR => self.exec_ldr_str(sysbus, insn),
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ArmFormat::MSR_REG => self.exec_msr_reg(sysbus, insn),
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ArmFormat::BX => self.exec_bx(bus, insn),
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ArmFormat::B_BL => self.exec_b_bl(bus, insn),
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ArmFormat::DP => self.exec_data_processing(bus, insn),
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ArmFormat::SWI => self.exec_swi(bus, insn),
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ArmFormat::LDR_STR => self.exec_ldr_str(bus, insn),
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ArmFormat::MSR_REG => self.exec_msr_reg(bus, insn),
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_ => Err(CpuError::UnimplementedCpuInstruction(
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insn.pc,
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insn.raw,
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@ -39,33 +31,18 @@ impl Core {
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}
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/// Cycles 2S+1N
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fn exec_b_bl(
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&mut self,
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sysbus: &mut Bus,
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insn: ArmInstruction,
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) -> CpuResult<CpuPipelineAction> {
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fn exec_b_bl(&mut self, bus: &mut Bus, insn: ArmInstruction) -> CpuResult<CpuPipelineAction> {
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if insn.link_flag() {
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self.set_reg(14, (insn.pc + (self.word_size() as u32)) & !0b1);
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}
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// +1N
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self.add_cycles(self.pc, sysbus, NonSeq + MemoryAccess32);
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self.pc = (self.pc as i32).wrapping_add(insn.branch_offset()) as u32 & !1;
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// +2S
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self.add_cycles(self.pc, sysbus, Seq + MemoryAccess32);
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self.add_cycles(
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self.pc + (self.word_size() as u32),
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sysbus,
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Seq + MemoryAccess32,
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);
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Ok(CpuPipelineAction::Flush)
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}
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/// Cycles 2S+1N
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fn exec_bx(&mut self, sysbus: &mut Bus, insn: ArmInstruction) -> CpuResult<CpuPipelineAction> {
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fn exec_bx(&mut self, bus: &mut Bus, insn: ArmInstruction) -> CpuResult<CpuPipelineAction> {
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let rn = self.get_reg(insn.rn());
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if rn.bit(0) {
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self.cpsr.set_state(CpuState::THUMB);
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@ -73,34 +50,19 @@ impl Core {
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self.cpsr.set_state(CpuState::ARM);
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}
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// +1N
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self.add_cycles(self.pc, sysbus, NonSeq + MemoryAccess32);
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self.pc = rn & !1;
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// +2S
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self.add_cycles(self.pc, sysbus, Seq + MemoryAccess32);
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self.add_cycles(
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self.pc + (self.word_size() as u32),
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sysbus,
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Seq + MemoryAccess32,
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);
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Ok(CpuPipelineAction::Flush)
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}
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fn exec_swi(
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&mut self,
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_sysbus: &mut Bus,
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_insn: ArmInstruction,
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) -> CpuResult<CpuPipelineAction> {
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fn exec_swi(&mut self, _bus: &mut Bus, _insn: ArmInstruction) -> CpuResult<CpuPipelineAction> {
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self.exception(Exception::SoftwareInterrupt);
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Ok(CpuPipelineAction::Flush)
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}
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fn exec_msr_reg(
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&mut self,
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sysbus: &mut Bus,
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bus: &mut Bus,
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insn: ArmInstruction,
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) -> CpuResult<CpuPipelineAction> {
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let new_psr = RegPSR::new(self.get_reg(insn.rm()));
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@ -117,7 +79,6 @@ impl Core {
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}
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self.cpsr = new_psr;
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}
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self.add_cycles(insn.pc, sysbus, Seq + MemoryAccess32);
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Ok(CpuPipelineAction::IncPC)
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}
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@ -204,7 +165,7 @@ impl Core {
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/// Add x=1I cycles if Op2 shifted-by-register. Add y=1S+1N cycles if Rd=R15.
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fn exec_data_processing(
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&mut self,
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sysbus: &mut Bus,
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bus: &mut Bus,
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insn: ArmInstruction,
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) -> CpuResult<CpuPipelineAction> {
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// TODO handle carry flag
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@ -219,10 +180,6 @@ impl Core {
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let op2 = insn.operand2()?;
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let rd = insn.rd();
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if rd == REG_PC {
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// +1N
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self.add_cycles(self.pc, sysbus, NonSeq + MemoryAccess32);
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}
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let op2: i32 = match op2 {
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ArmShiftedValue::RotatedImmediate(immediate, rotate) => {
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@ -246,17 +203,9 @@ impl Core {
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self.set_reg(rd, result as u32);
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if rd == REG_PC {
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pipeline_action = CpuPipelineAction::Flush;
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// +1S
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self.add_cycles(self.pc, sysbus, Seq + MemoryAccess32);
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}
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}
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// +1S
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self.add_cycles(
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self.pc + (self.word_size() as u32),
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sysbus,
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Seq + MemoryAccess32,
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);
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Ok(pipeline_action)
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}
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@ -289,7 +238,7 @@ impl Core {
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/// For LDR, add y=1S+1N if Rd=R15.
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fn exec_ldr_str(
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&mut self,
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sysbus: &mut Bus,
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bus: &mut Bus,
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insn: ArmInstruction,
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) -> CpuResult<CpuPipelineAction> {
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if insn.write_back_flag() && insn.rd() == insn.rn() {
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@ -316,19 +265,11 @@ impl Core {
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if insn.load_flag() {
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let data = if insn.transfer_size() == 1 {
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// +1N
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self.add_cycles(addr, sysbus, NonSeq + MemoryAccess8);
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sysbus.read_8(addr) as u32
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self.load_8(addr, bus) as u32
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} else {
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// +1N
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self.add_cycles(addr, sysbus, NonSeq + MemoryAccess32);
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sysbus.read_32(addr)
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self.load_32(addr, bus)
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};
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// +1S
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self.add_cycles(
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self.pc + (self.word_size() as u32),
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sysbus,
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Seq + MemoryAccess32,
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);
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self.set_reg(insn.rd(), data);
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@ -336,27 +277,15 @@ impl Core {
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self.add_cycle();
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// +y
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if insn.rd() == REG_PC {
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// +1S
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self.add_cycles(self.pc, sysbus, Seq + MemoryAccess32);
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// +1N
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self.add_cycles(
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self.pc + (self.word_size() as u32),
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sysbus,
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NonSeq + MemoryAccess32,
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);
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pipeline_action = CpuPipelineAction::Flush;
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}
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} else {
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self.add_cycles(addr, sysbus, NonSeq + MemoryAccess32);
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let value = self.get_reg(insn.rd());
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if insn.transfer_size() == 1 {
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// +1N
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self.add_cycles(dest, sysbus, NonSeq + MemoryAccess8);
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sysbus.write_8(addr, value as u8).expect("bus error");
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self.store_8(addr, value as u8, bus);
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} else {
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// +1N
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self.add_cycles(dest, sysbus, NonSeq + MemoryAccess32);
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sysbus.write_32(addr, value).expect("bus error");
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self.store_32(addr, value, bus);
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};
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}
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@ -538,17 +538,17 @@ mod tests {
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core.set_reg(REG_SP, 0);
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let bytes = vec![
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/* 0: */ 0xaa, 0xbb, 0xcc, 0xdd,
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/* 4: */ 0xaa, 0xbb, 0xcc, 0xdd,
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/* 8: */ 0xaa, 0xbb, 0xcc, 0xdd,
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/* c: */ 0xaa, 0xbb, 0xcc, 0xdd,
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/* 0: */ 0xaa, 0xbb, 0xcc, 0xdd, /* 4: */ 0xaa, 0xbb, 0xcc, 0xdd,
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/* 8: */ 0xaa, 0xbb, 0xcc, 0xdd, /* c: */ 0xaa, 0xbb, 0xcc, 0xdd,
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/* 10: */ 0xaa, 0xbb, 0xcc, 0xdd,
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];
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice());
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assert_ne!(mem.read_32(core.get_reg(REG_SP) + 0x10), 0x12345678);
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assert_eq!(core.exec_arm(&mut mem, decoded), Ok(CpuPipelineAction::IncPC));
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assert_eq!(
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core.exec_arm(&mut mem, decoded),
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Ok(CpuPipelineAction::IncPC)
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);
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assert_eq!(mem.read_32(core.get_reg(REG_SP) + 0x10), 0x12345678);
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}
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}
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@ -1,14 +1,31 @@
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use super::Addr;
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use std::fmt;
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use std::io;
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use std::ops::Add;
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use byteorder::{LittleEndian, ReadBytesExt, WriteBytesExt};
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use super::Addr;
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#[derive(Debug)]
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pub enum MemoryAccessType {
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NonSeq,
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Seq,
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}
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impl fmt::Display for MemoryAccessType {
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fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
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write!(
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f,
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"{}",
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match self {
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MemoryAccessType::NonSeq => "N",
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MemoryAccessType::Seq => "S",
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}
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)
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}
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}
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#[derive(Debug)]
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pub enum MemoryAccessWidth {
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MemoryAccess8,
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MemoryAccess16,
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@ -23,8 +40,15 @@ impl Add<MemoryAccessWidth> for MemoryAccessType {
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}
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}
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#[derive(Debug)]
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pub struct MemoryAccess(pub MemoryAccessType, pub MemoryAccessWidth);
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impl fmt::Display for MemoryAccess {
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fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
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write!(f, "{}-Cycle ({:?})", self.0, self.1)
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}
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}
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pub trait Bus {
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fn read_32(&self, addr: Addr) -> u32 {
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self.get_bytes(addr).read_u32::<LittleEndian>().unwrap()
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@ -1,16 +1,12 @@
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use std::convert::TryFrom;
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use std::fmt;
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use std::ops::Add;
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use ansi_term::{Colour, Style};
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use num_traits::Num;
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use crate::sysbus::SysBus;
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pub use super::exception::Exception;
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use super::{
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arm::*,
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bus::{Bus, MemoryAccess, MemoryAccessType::*, MemoryAccessWidth::*},
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bus::{Bus, MemoryAccess, MemoryAccessType, MemoryAccessType::*, MemoryAccessWidth::*},
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psr::RegPSR,
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reg_string,
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thumb::ThumbInstruction,
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@ -84,6 +80,8 @@ pub struct Core {
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// store the gpr before executing an instruction to show diff in the Display impl
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gpr_previous: [u32; 15],
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memreq: Addr,
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pub verbose: bool,
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}
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@ -98,6 +96,7 @@ pub type CpuExecResult = CpuResult<CpuPipelineAction>;
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impl Core {
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pub fn new() -> Core {
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Core {
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memreq: 0xffff_0000, // set memreq to an invalid addr so the first load cycle will be non-sequential
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..Default::default()
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}
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}
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@ -157,8 +156,10 @@ impl Core {
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}
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self.map_banked_registers(curr_mode, new_mode);
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let next_index = new_mode.bank_index();
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self.gpr_banked_r14[next_index] = self.pc.wrapping_sub(self.word_size() as u32).wrapping_add(4);
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self.gpr_banked_r14[next_index] = self
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.pc
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.wrapping_sub(self.word_size() as u32)
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.wrapping_add(4);
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}
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/// Resets the cpu
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@ -182,11 +183,62 @@ impl Core {
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}
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pub fn add_cycle(&mut self) {
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println!("<cycle I-Cyclel> total: {}", self.cycles);
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self.cycles += 1;
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}
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pub fn add_cycles(&mut self, addr: Addr, sysbus: &Bus, access: MemoryAccess) {
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self.cycles += sysbus.get_cycles(addr, access);
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pub fn add_cycles(&mut self, addr: Addr, bus: &Bus, access: MemoryAccess) {
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println!("<cycle {:#x} {}> total: {}", addr, access, self.cycles);
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self.cycles += bus.get_cycles(addr, access);
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}
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pub fn cycle_type(&self, addr: Addr) -> MemoryAccessType {
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if addr == self.memreq || addr == self.memreq + (self.word_size() as Addr) {
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Seq
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} else {
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NonSeq
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}
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}
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pub fn load_32(&mut self, addr: Addr, bus: &mut Bus) -> u32 {
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self.add_cycles(addr, bus, self.cycle_type(addr) + MemoryAccess32);
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self.memreq = addr;
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bus.read_32(addr)
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}
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pub fn load_16(&mut self, addr: Addr, bus: &mut Bus) -> u16 {
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let cycle_type = self.cycle_type(addr);
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self.add_cycles(addr, bus, cycle_type + MemoryAccess16);
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self.memreq = addr;
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bus.read_16(addr)
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}
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pub fn load_8(&mut self, addr: Addr, bus: &mut Bus) -> u8 {
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let cycle_type = self.cycle_type(addr);
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self.add_cycles(addr, bus, cycle_type + MemoryAccess8);
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self.memreq = addr;
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bus.read_8(addr)
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}
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pub fn store_32(&mut self, addr: Addr, value: u32, bus: &mut Bus) {
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let cycle_type = self.cycle_type(addr);
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self.add_cycles(addr, bus, cycle_type + MemoryAccess32);
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self.memreq = addr;
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bus.write_32(addr, value).expect("store_32 error");
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}
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pub fn store_16(&mut self, addr: Addr, value: u16, bus: &mut Bus) {
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let cycle_type = self.cycle_type(addr);
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self.add_cycles(addr, bus, cycle_type + MemoryAccess16);
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self.memreq = addr;
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bus.write_16(addr, value).expect("store_16 error");
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}
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pub fn store_8(&mut self, addr: Addr, value: u8, bus: &mut Bus) {
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let cycle_type = self.cycle_type(addr);
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self.add_cycles(addr, bus, cycle_type + MemoryAccess8);
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self.memreq = addr;
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bus.write_8(addr, value).expect("store_16 error");
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}
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pub fn check_arm_cond(&self, cond: ArmCond) -> bool {
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@ -212,10 +264,11 @@ impl Core {
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fn step_thumb(
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&mut self,
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sysbus: &mut Bus,
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bus: &mut Bus,
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) -> CpuResult<(Option<DecodedInstruction>, CpuPipelineAction)> {
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// fetch
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let new_fetched = sysbus.read_16(self.pc);
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// let new_fetched = bus.read_16(self.pc);
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let new_fetched = self.load_16(self.pc, bus);
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// decode
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let new_decoded = match self.pipeline_thumb.fetched {
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@ -230,7 +283,7 @@ impl Core {
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let result = match self.pipeline_thumb.decoded {
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Some(d) => {
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self.gpr_previous = self.get_registers();
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let action = self.exec_thumb(sysbus, d)?;
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let action = self.exec_thumb(bus, d)?;
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Ok((Some(DecodedInstruction::Thumb(d)), action))
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}
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None => Ok((None, CpuPipelineAction::IncPC)),
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@ -246,10 +299,10 @@ impl Core {
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fn step_arm(
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&mut self,
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sysbus: &mut Bus,
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bus: &mut Bus,
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) -> CpuResult<(Option<DecodedInstruction>, CpuPipelineAction)> {
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// fetch
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let new_fetched = sysbus.read_32(self.pc);
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// let new_fetched = bus.read_32(self.pc);
|
||||
let new_fetched = self.load_32(self.pc, bus);
|
||||
|
||||
// decode
|
||||
let new_decoded = match self.pipeline_arm.fetched {
|
||||
|
|
@ -264,7 +317,7 @@ impl Core {
|
|||
let result = match self.pipeline_arm.decoded {
|
||||
Some(d) => {
|
||||
self.gpr_previous = self.get_registers();
|
||||
let action = self.exec_arm(sysbus, d)?;
|
||||
let action = self.exec_arm(bus, d)?;
|
||||
Ok((Some(DecodedInstruction::Arm(d)), action))
|
||||
}
|
||||
None => Ok((None, CpuPipelineAction::IncPC)),
|
||||
|
|
@ -280,10 +333,10 @@ impl Core {
|
|||
|
||||
/// Perform a pipeline step
|
||||
/// If an instruction was executed in this step, return it.
|
||||
pub fn step(&mut self, sysbus: &mut Bus) -> CpuResult<Option<DecodedInstruction>> {
|
||||
pub fn step(&mut self, bus: &mut Bus) -> CpuResult<Option<DecodedInstruction>> {
|
||||
let (executed_instruction, pipeline_action) = match self.cpsr.state() {
|
||||
CpuState::ARM => self.step_arm(sysbus),
|
||||
CpuState::THUMB => self.step_thumb(sysbus),
|
||||
CpuState::ARM => self.step_arm(bus),
|
||||
CpuState::THUMB => self.step_thumb(bus),
|
||||
}?;
|
||||
|
||||
match pipeline_action {
|
||||
|
|
@ -328,9 +381,9 @@ impl Core {
|
|||
/// A step that returns only once an instruction was executed.
|
||||
/// Returns the address of PC before executing an instruction,
|
||||
/// and the address of the next instruction to be executed;
|
||||
pub fn step_debugger(&mut self, sysbus: &mut Bus) -> CpuResult<DecodedInstruction> {
|
||||
pub fn step_debugger(&mut self, bus: &mut Bus) -> CpuResult<DecodedInstruction> {
|
||||
loop {
|
||||
if let Some(i) = self.step(sysbus)? {
|
||||
if let Some(i) = self.step(bus)? {
|
||||
return Ok(i);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -92,11 +92,7 @@ impl ThumbInstruction {
|
|||
}
|
||||
|
||||
fn fmt_thumb_add_sp(&self, f: &mut fmt::Formatter) -> fmt::Result {
|
||||
write!(
|
||||
f,
|
||||
"add\tsp, #{imm:x}",
|
||||
imm = self.sword7()
|
||||
)
|
||||
write!(f, "add\tsp, #{imm:x}", imm = self.sword7())
|
||||
}
|
||||
|
||||
fn fmt_thumb_push_pop(&self, f: &mut fmt::Formatter) -> fmt::Result {
|
||||
|
|
@ -110,7 +106,7 @@ impl ThumbInstruction {
|
|||
for reg in register_list {
|
||||
has_reg = true;
|
||||
write!(f, ", {}", reg_string(reg))?;
|
||||
};
|
||||
}
|
||||
if self.flag(ThumbInstruction::FLAG_R) {
|
||||
let r = if self.is_load() { "pc" } else { "lr" };
|
||||
if has_reg {
|
||||
|
|
|
|||
|
|
@ -1,20 +1,20 @@
|
|||
use crate::arm7tdmi::arm::*;
|
||||
use crate::arm7tdmi::bus::{Bus, MemoryAccessType::*, MemoryAccessWidth::*};
|
||||
use crate::arm7tdmi::cpu::{Core, CpuExecResult, CpuPipelineAction};
|
||||
use crate::arm7tdmi::{Addr, REG_PC, REG_LR, REG_SP, CpuState, reg_string};
|
||||
use crate::arm7tdmi::{reg_string, Addr, CpuState, REG_LR, REG_PC, REG_SP};
|
||||
|
||||
use super::*;
|
||||
fn push(cpu: &mut Core, bus: &mut Bus, r: usize) {
|
||||
cpu.gpr[REG_SP] -= 4;
|
||||
let stack_addr = cpu.gpr[REG_SP];
|
||||
bus.write_32(stack_addr, cpu.get_reg(r)).expect("bus error");
|
||||
}
|
||||
cpu.gpr[REG_SP] -= 4;
|
||||
let stack_addr = cpu.gpr[REG_SP];
|
||||
cpu.store_32(stack_addr, cpu.get_reg(r), bus)
|
||||
}
|
||||
fn pop(cpu: &mut Core, bus: &mut Bus, r: usize) {
|
||||
let stack_addr = cpu.gpr[REG_SP];
|
||||
let val = bus.read_32(stack_addr);
|
||||
cpu.set_reg(r, val);
|
||||
cpu.gpr[REG_SP] = stack_addr + 4;
|
||||
}
|
||||
let stack_addr = cpu.gpr[REG_SP];
|
||||
let val = cpu.load_32(stack_addr, bus);
|
||||
cpu.set_reg(r, val);
|
||||
cpu.gpr[REG_SP] = stack_addr + 4;
|
||||
}
|
||||
|
||||
impl Core {
|
||||
fn exec_thumb_add_sub(&mut self, bus: &mut Bus, insn: ThumbInstruction) -> CpuExecResult {
|
||||
|
|
@ -34,12 +34,7 @@ impl Core {
|
|||
if let Some(result) = result {
|
||||
self.set_reg(insn.rd(), result as u32);
|
||||
}
|
||||
// +1S
|
||||
self.add_cycles(
|
||||
insn.pc + (self.word_size() as u32),
|
||||
bus,
|
||||
Seq + MemoryAccess32,
|
||||
);
|
||||
|
||||
Ok(CpuPipelineAction::IncPC)
|
||||
}
|
||||
|
||||
|
|
@ -55,21 +50,12 @@ impl Core {
|
|||
if let Some(result) = result {
|
||||
self.set_reg(insn.rd(), result as u32);
|
||||
}
|
||||
// +1S
|
||||
self.add_cycles(
|
||||
insn.pc + (self.word_size() as u32),
|
||||
bus,
|
||||
Seq + MemoryAccess16,
|
||||
);
|
||||
|
||||
Ok(CpuPipelineAction::IncPC)
|
||||
}
|
||||
|
||||
/// Cycles 2S+1N
|
||||
fn exec_thumb_bx(
|
||||
&mut self,
|
||||
bus: &mut Bus,
|
||||
insn: ThumbInstruction,
|
||||
) -> CpuExecResult {
|
||||
fn exec_thumb_bx(&mut self, bus: &mut Bus, insn: ThumbInstruction) -> CpuExecResult {
|
||||
let src_reg = if insn.flag(ThumbInstruction::FLAG_H2) {
|
||||
insn.rs() + 8
|
||||
} else {
|
||||
|
|
@ -83,19 +69,8 @@ impl Core {
|
|||
self.cpsr.set_state(CpuState::ARM);
|
||||
}
|
||||
|
||||
// +1N
|
||||
self.add_cycles(self.pc, bus, NonSeq + MemoryAccess32);
|
||||
|
||||
self.pc = addr & !1;
|
||||
|
||||
// +2S
|
||||
self.add_cycles(self.pc, bus, Seq + MemoryAccess32);
|
||||
self.add_cycles(
|
||||
self.pc + (self.word_size() as u32),
|
||||
bus,
|
||||
Seq + MemoryAccess32,
|
||||
);
|
||||
|
||||
Ok(CpuPipelineAction::Flush)
|
||||
}
|
||||
|
||||
|
|
@ -108,21 +83,14 @@ impl Core {
|
|||
self.exec_thumb_bx(bus, insn)
|
||||
} else {
|
||||
unimplemented!("Sorry, I'm tired");
|
||||
Ok(CpuPipelineAction::IncPC)
|
||||
// Ok(CpuPipelineAction::IncPC)
|
||||
}
|
||||
}
|
||||
|
||||
fn exec_thumb_ldr_pc(&mut self, bus: &mut Bus, insn: ThumbInstruction) -> CpuExecResult {
|
||||
let addr = (insn.pc & !0b10) + 4 + (insn.word8() as Addr);
|
||||
let data = bus.read_32(addr);
|
||||
// +1N
|
||||
self.add_cycles(addr, bus, NonSeq + MemoryAccess32);
|
||||
// +1S
|
||||
self.add_cycles(
|
||||
insn.pc + (self.word_size() as u32),
|
||||
bus,
|
||||
Seq + MemoryAccess16,
|
||||
);
|
||||
let data = self.load_32(addr, bus);
|
||||
|
||||
self.set_reg(insn.rd(), data);
|
||||
// +1I
|
||||
self.add_cycle();
|
||||
|
|
@ -140,37 +108,21 @@ impl Core {
|
|||
.wrapping_add(self.get_reg(insn.ro()));
|
||||
if insn.is_load() {
|
||||
let data = if insn.is_transfering_bytes() {
|
||||
// +1N
|
||||
self.add_cycles(addr, bus, NonSeq + MemoryAccess8);
|
||||
bus.read_8(addr) as u32
|
||||
self.load_8(addr, bus) as u32
|
||||
} else {
|
||||
// +1N
|
||||
self.add_cycles(addr, bus, NonSeq + MemoryAccess32);
|
||||
bus.read_32(addr)
|
||||
self.load_32(addr, bus)
|
||||
};
|
||||
|
||||
// +1S
|
||||
self.add_cycles(
|
||||
insn.pc + (self.word_size() as u32),
|
||||
bus,
|
||||
Seq + MemoryAccess32,
|
||||
);
|
||||
|
||||
self.set_reg(insn.rd(), data);
|
||||
|
||||
// +1I
|
||||
self.add_cycle();
|
||||
} else {
|
||||
self.add_cycles(addr, bus, NonSeq + MemoryAccess32);
|
||||
let value = self.get_reg(insn.rd());
|
||||
if insn.is_transfering_bytes() {
|
||||
// +1N
|
||||
self.add_cycles(addr, bus, NonSeq + MemoryAccess8);
|
||||
bus.write_8(addr, value as u8).expect("bus error");
|
||||
self.store_8(addr, value as u8, bus);
|
||||
} else {
|
||||
// +1N
|
||||
self.add_cycles(addr, bus, NonSeq + MemoryAccess32);
|
||||
bus.write_32(addr, value).expect("bus error");
|
||||
self.store_32(addr, value, bus);
|
||||
};
|
||||
}
|
||||
|
||||
|
|
@ -186,27 +138,16 @@ impl Core {
|
|||
if let Some(result) = result {
|
||||
self.gpr[REG_SP] = result as u32;
|
||||
}
|
||||
// +1S
|
||||
self.add_cycles(
|
||||
insn.pc + (self.word_size() as u32),
|
||||
bus,
|
||||
Seq + MemoryAccess32,
|
||||
);
|
||||
|
||||
Ok(CpuPipelineAction::IncPC)
|
||||
}
|
||||
|
||||
fn exec_thumb_push_pop(
|
||||
&mut self,
|
||||
bus: &mut Bus,
|
||||
insn: ThumbInstruction,
|
||||
) -> CpuExecResult {
|
||||
fn exec_thumb_push_pop(&mut self, bus: &mut Bus, insn: ThumbInstruction) -> CpuExecResult {
|
||||
// (From GBATEK) Execution Time: nS+1N+1I (POP), (n+1)S+2N+1I (POP PC), or (n-1)S+2N (PUSH).
|
||||
|
||||
let is_pop = insn.is_load();
|
||||
let mut pipeline_action = CpuPipelineAction::IncPC;
|
||||
|
||||
self.add_cycles(insn.pc, bus, NonSeq + MemoryAccess16);
|
||||
|
||||
let pc_lr_flag = insn.flag(ThumbInstruction::FLAG_R);
|
||||
let rlist = insn.register_list();
|
||||
if is_pop {
|
||||
|
|
@ -216,62 +157,30 @@ impl Core {
|
|||
if pc_lr_flag {
|
||||
pop(self, bus, REG_PC);
|
||||
pipeline_action = CpuPipelineAction::Flush;
|
||||
self.add_cycles(
|
||||
self.pc,
|
||||
bus,
|
||||
Seq + MemoryAccess32
|
||||
);
|
||||
self.add_cycles(
|
||||
self.pc + (self.word_size() as u32),
|
||||
bus,
|
||||
NonSeq + MemoryAccess16
|
||||
);
|
||||
}
|
||||
self.add_cycle();
|
||||
} else {
|
||||
self.add_cycles(
|
||||
self.gpr[REG_SP],
|
||||
bus,
|
||||
NonSeq + MemoryAccess32
|
||||
);
|
||||
if pc_lr_flag {
|
||||
push(self, bus, REG_LR);
|
||||
}
|
||||
for r in rlist.into_iter().rev() {
|
||||
push(self, bus ,r);
|
||||
push(self, bus, r);
|
||||
}
|
||||
self.add_cycles(self.gpr[REG_SP], bus, NonSeq + MemoryAccess32);
|
||||
}
|
||||
|
||||
Ok(CpuPipelineAction::IncPC)
|
||||
Ok(pipeline_action)
|
||||
}
|
||||
|
||||
fn exec_thumb_branch_with_cond(
|
||||
&mut self,
|
||||
bus: &mut Bus,
|
||||
_bus: &mut Bus,
|
||||
insn: ThumbInstruction,
|
||||
) -> CpuExecResult {
|
||||
if !self.check_arm_cond(insn.cond()) {
|
||||
self.add_cycles(
|
||||
insn.pc + (self.word_size() as u32),
|
||||
bus,
|
||||
Seq + MemoryAccess16,
|
||||
);
|
||||
Ok(CpuPipelineAction::IncPC)
|
||||
} else {
|
||||
// +1N
|
||||
self.add_cycles(insn.pc, bus, NonSeq + MemoryAccess32);
|
||||
let offset = insn.offset8() as i8 as i32;
|
||||
self.pc = (insn.pc as i32).wrapping_add(offset) as u32;
|
||||
|
||||
// +2S
|
||||
self.add_cycles(self.pc, bus, Seq + MemoryAccess32);
|
||||
self.add_cycles(
|
||||
self.pc + (self.word_size() as u32),
|
||||
bus,
|
||||
Seq + MemoryAccess32,
|
||||
);
|
||||
|
||||
Ok(CpuPipelineAction::Flush)
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -325,12 +325,9 @@ mod tests {
|
|||
let insn = ThumbInstruction::decode(0x4801, 0x6).unwrap();
|
||||
|
||||
let bytes = vec![
|
||||
/* 0: */ 0x00, 0x00,
|
||||
/* 2: */ 0x00, 0x00,
|
||||
/* 4: */ 0x00, 0x00,
|
||||
/* 6: <pc> */ 0x00, 0x00,
|
||||
/* 8: */ 0x00, 0x00, 0x00, 0x00,
|
||||
/* c: */ 0x78, 0x56, 0x34, 0x12,
|
||||
/* 0: */ 0x00, 0x00, /* 2: */ 0x00, 0x00, /* 4: */ 0x00, 0x00,
|
||||
/* 6: <pc> */ 0x00, 0x00, /* 8: */ 0x00, 0x00, 0x00, 0x00,
|
||||
/* c: */ 0x78, 0x56, 0x34, 0x12,
|
||||
];
|
||||
let mut mem = BoxedMemory::new(bytes.into_boxed_slice());
|
||||
let mut core = Core::new();
|
||||
|
|
|
|||
Reference in a new issue