Fix exceptions and dataprocess mode change
Former-commit-id: 5892131496904b621398212b9dfc077242fa9557
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7501adfd12
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c0d437b1a1
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@ -180,10 +180,21 @@ impl Core {
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let rd = insn.rd();
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if let Some(result) = self.alu(opcode, op1, op2, set_flags) {
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self.set_reg(rd, result as u32);
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if rd == REG_PC {
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// TODO move this code into a function
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let old_mode = self.cpsr.mode();
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if let Some(index) = old_mode.spsr_index() {
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let new_psr = self.spsr[index];
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if old_mode != new_psr.mode() {
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self.change_mode(new_psr.mode());
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}
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self.cpsr = new_psr;
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} else {
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panic!("tried to change spsr from invalid mode {}", old_mode)
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}
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self.flush_pipeline();
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}
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self.set_reg(rd, result as u32);
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}
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Ok(())
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@ -121,11 +121,8 @@ impl Core {
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self.spsr[index] = self.cpsr;
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}
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self.map_banked_registers(curr_mode, new_mode);
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let next_index = new_mode.bank_index();
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self.gpr_banked_r14[next_index] = self
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.pc
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.wrapping_sub(self.word_size() as u32)
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.wrapping_add(4);
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// let next_index = new_mode.bank_index();
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// self.gpr_banked_r14[next_index] = self.get_next_pc();
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}
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/// Resets the cpu
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@ -1,5 +1,5 @@
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use super::REG_LR;
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use super::{cpu::Core, CpuMode, CpuState};
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use colored::*;
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#[derive(Debug, Clone, Copy, PartialEq)]
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@ -35,10 +35,18 @@ impl Core {
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let vector = e as u32;
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let new_mode = CpuMode::from(e);
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if self.verbose {
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println!("{}: {:?}, new_mode: {:?}", "Exception".cyan(), e, new_mode);
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println!(
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"{}: {:?}, pc: {:#x}, new_mode: {:?}",
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"Exception".cyan(),
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e,
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self.pc,
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new_mode
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);
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}
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self.change_mode(new_mode);
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self.gpr[REG_LR] = self.get_next_pc() + (self.word_size() as u32);
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// Set appropriate CPSR bits
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self.cpsr.set_state(CpuState::ARM);
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self.cpsr.set_mode(new_mode);
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@ -262,11 +262,7 @@ impl ThumbInstruction {
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}
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fn fmt_thumb_swi(&self, f: &mut fmt::Formatter) -> fmt::Result {
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write!(
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f,
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"swi\t{value:#x}",
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value = self.raw & 0xff,
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)
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write!(f, "swi\t{value:#x}", value = self.raw & 0xff,)
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}
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fn fmt_thumb_branch(&self, f: &mut fmt::Formatter) -> fmt::Result {
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