Impl more thumb, Fix more things, the usual
Former-commit-id: 02f1898bfd8dd50519f103bb367e358fc55c46e7
This commit is contained in:
Michel Heily
parent
6dd48c6238
commit
c2685c14d7
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@ -98,7 +98,7 @@ impl Core {
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val.wrapping_shl(amount)
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}
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ArmShiftType::LSR => {
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if amount < 32 {
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if 0 < amount && amount < 32 {
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self.cpsr.set_C(val.wrapping_shr(amount - 1) & 1 == 1);
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} else {
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self.cpsr.set_C(false);
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@ -106,7 +106,7 @@ impl Core {
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(val as u32).wrapping_shr(amount) as i32
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}
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ArmShiftType::ASR => {
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if amount < 32 {
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if 0 < amount && amount < 32 {
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self.cpsr.set_C(val.wrapping_shr(amount - 1) & 1 == 1);
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} else {
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self.cpsr.set_C(val >> 31 == 1);
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@ -374,7 +374,12 @@ impl Core {
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addr = addr.wrapping_add(step);
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}
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self.store_32(addr as Addr, self.get_reg(r), bus);
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let val = if r == REG_PC {
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insn.pc + 12
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} else {
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self.get_reg(r)
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};
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self.store_32(addr as Addr, val, bus);
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if !full {
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addr = addr.wrapping_add(step);
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@ -452,7 +452,6 @@ mod tests {
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let bytes = vec![];
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice());
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// swi #0x1337
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let decoded = ArmInstruction::decode(0xef001337, 0).unwrap();
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assert_eq!(decoded.fmt, ArmFormat::SWI);
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@ -547,10 +546,12 @@ mod tests {
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core.gpr[2] = 0;
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let bytes = vec![
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/* 00h: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 10h: */ 0x00, 0x00, 0x00, 0x00, 0x37, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 20h: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 30h: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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/* 00h: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, /* 10h: */ 0x00, 0x00, 0x00, 0x00, 0x37, 0x13, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 20h: */ 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 30h: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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];
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice());
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@ -590,10 +591,12 @@ mod tests {
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core.gpr[2] = 0xabababab;
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let bytes = vec![
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/* 00h: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 10h: */ 0x00, 0x00, 0x00, 0x00, 0x37, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 20h: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 30h: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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/* 00h: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, /* 10h: */ 0x00, 0x00, 0x00, 0x00, 0x37, 0x13, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 20h: */ 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 30h: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00,
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];
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let mut mem = BoxedMemory::new(bytes.into_boxed_slice());
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@ -193,7 +193,7 @@ impl Core {
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}
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pub fn cycle_type(&self, addr: Addr) -> MemoryAccessType {
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if addr == self.memreq || addr == self.memreq + (self.word_size() as Addr) {
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if addr == self.memreq || addr == self.memreq.wrapping_add(self.word_size() as Addr) {
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Seq
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} else {
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NonSeq
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@ -97,6 +97,28 @@ impl ThumbInstruction {
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)
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}
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fn fmt_thumb_ldr_str_shb(&self, f: &mut fmt::Formatter) -> fmt::Result {
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write!(
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f,
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"{op}\t{Rd}, [{Rb}, {Ro}]",
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op = {
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match (
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self.flag(ThumbInstruction::FLAG_SIGN_EXTEND),
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self.flag(ThumbInstruction::FLAG_HALFWORD),
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) {
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(false, false) => "strh",
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(false, true) => "ldrh",
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(true, false) => "ldsb",
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(true, true) => "ldsh",
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_ => panic!("invalid flags"),
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}
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},
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Rd = reg_string(self.rd()),
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Rb = reg_string(self.rb()),
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Ro = reg_string(self.ro()),
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)
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}
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fn fmt_thumb_ldr_str_imm_offset(&self, f: &mut fmt::Formatter) -> fmt::Result {
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write!(
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f,
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@ -141,6 +163,20 @@ impl ThumbInstruction {
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)
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}
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fn fmt_thumb_ldr_address(&self, f: &mut fmt::Formatter) -> fmt::Result {
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write!(
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f,
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"add\t{Rd}, {r}, #{Imm:#x}",
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Rd = reg_string(self.rd()),
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r = if self.flag(ThumbInstruction::FLAG_SP) {
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"sp"
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} else {
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"pc"
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},
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Imm = self.word8(),
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)
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}
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fn fmt_thumb_add_sub(&self, f: &mut fmt::Formatter) -> fmt::Result {
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let operand = if self.is_immediate_operand() {
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format!("#{:x}", self.raw.bit_range(6..9))
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@ -150,7 +186,7 @@ impl ThumbInstruction {
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write!(
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f,
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"{op}\t{Rd}, [{Rs}, {operand}]",
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"{op}\t{Rd}, {Rs}, {operand}",
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op = if self.is_subtract() { "sub" } else { "add" },
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Rd = reg_string(self.rd()),
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Rs = reg_string(self.rs()),
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@ -185,6 +221,26 @@ impl ThumbInstruction {
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write!(f, "}}")
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}
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fn fmt_thumb_ldm_stm(&self, f: &mut fmt::Formatter) -> fmt::Result {
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write!(
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f,
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"{op}\t{Rb}!, {{",
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op = if self.is_load() { "ldm" } else { "stm" },
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Rb = reg_string(self.rb()),
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)?;
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let mut register_list = self.register_list().into_iter();
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let mut has_reg = false;
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if let Some(reg) = register_list.next() {
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write!(f, "{}", reg_string(reg))?;
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has_reg = true;
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}
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for reg in register_list {
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has_reg = true;
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write!(f, ", {}", reg_string(reg))?;
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}
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write!(f, "}}")
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}
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fn fmt_thumb_branch_with_cond(&self, f: &mut fmt::Formatter) -> fmt::Result {
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write!(
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f,
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@ -231,11 +287,14 @@ impl fmt::Display for ThumbInstruction {
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ThumbFormat::HiRegOpOrBranchExchange => self.fmt_thumb_high_reg_op_or_bx(f),
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ThumbFormat::LdrPc => self.fmt_thumb_ldr_pc(f),
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ThumbFormat::LdrStrRegOffset => self.fmt_thumb_ldr_str_reg_offset(f),
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ThumbFormat::LdrStrSHB => self.fmt_thumb_ldr_str_shb(f),
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ThumbFormat::LdrStrImmOffset => self.fmt_thumb_ldr_str_imm_offset(f),
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ThumbFormat::LdrStrHalfWord => self.fmt_thumb_ldr_str_halfword(f),
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ThumbFormat::LdrStrSp => self.fmt_thumb_ldr_str_sp(f),
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ThumbFormat::LdrAddress => self.fmt_thumb_ldr_address(f),
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ThumbFormat::AddSp => self.fmt_thumb_add_sp(f),
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ThumbFormat::PushPop => self.fmt_thumb_push_pop(f),
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ThumbFormat::LdmStm => self.fmt_thumb_ldm_stm(f),
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ThumbFormat::BranchConditional => self.fmt_thumb_branch_with_cond(f),
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ThumbFormat::Branch => self.fmt_thumb_branch(f),
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ThumbFormat::BranchLongWithLink => self.fmt_thumb_branch_long_with_link(f),
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@ -193,6 +193,43 @@ impl Core {
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self.do_exec_thumb_ldr_str(bus, insn, addr)
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}
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fn exec_thumb_ldr_str_shb(&mut self, bus: &mut Bus, insn: ThumbInstruction) -> CpuExecResult {
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let addr = self
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.get_reg(insn.rb())
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.wrapping_add(self.get_reg(insn.ro()));
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let rd = insn.rd();
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match (
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insn.flag(ThumbInstruction::FLAG_SIGN_EXTEND),
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insn.flag(ThumbInstruction::FLAG_HALFWORD),
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) {
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(false, false) =>
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/* strh */
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{
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self.store_16(addr, self.gpr[rd] as u16, bus)
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}
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(false, true) =>
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/* ldrh */
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{
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self.gpr[rd] = self.load_16(addr, bus) as u32
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}
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(true, false) =>
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/* ldsb */
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{
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let val = self.load_8(addr, bus) as i8 as i32 as u32;
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self.gpr[rd] = val;
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}
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(true, true) =>
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/* ldsh */
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{
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let val = self.load_16(addr, bus) as i16 as i32 as u32;
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self.gpr[rd] = val;
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}
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_ => panic!("invalid flags"),
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}
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Ok(CpuPipelineAction::IncPC)
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}
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fn exec_thumb_ldr_str_imm_offset(
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&mut self,
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bus: &mut Bus,
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@ -225,7 +262,25 @@ impl Core {
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}
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fn exec_thumb_ldr_str_sp(&mut self, bus: &mut Bus, insn: ThumbInstruction) -> CpuExecResult {
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let addr = (self.gpr[REG_SP] & !0b10) + 4 + (insn.word8() as Addr);
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let addr = self.gpr[REG_SP] + (insn.word8() as Addr);
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self.do_exec_thumb_ldr_str_with_addr(bus, insn, addr)
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}
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fn exec_thumb_ldr_address(&mut self, bus: &mut Bus, insn: ThumbInstruction) -> CpuExecResult {
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let addr = if insn.flag(ThumbInstruction::FLAG_SP) {
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self.gpr[REG_SP] + (insn.word8() as Addr)
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} else {
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(insn.pc & !0b10) + 4 + (insn.word8() as Addr)
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};
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self.do_exec_thumb_ldr_str_with_addr(bus, insn, addr)
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}
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fn do_exec_thumb_ldr_str_with_addr(
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&mut self,
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bus: &mut Bus,
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insn: ThumbInstruction,
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addr: Addr,
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) -> CpuExecResult {
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if insn.is_load() {
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let data = self.load_32(addr, bus);
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self.add_cycle();
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@ -263,6 +318,7 @@ impl Core {
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}
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if pc_lr_flag {
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pop(self, bus, REG_PC);
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self.pc = self.pc & !1;
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pipeline_action = CpuPipelineAction::Flush;
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}
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self.add_cycle();
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@ -278,6 +334,32 @@ impl Core {
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Ok(pipeline_action)
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}
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fn exec_thumb_ldm_stm(&mut self, bus: &mut Bus, insn: ThumbInstruction) -> CpuExecResult {
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// (From GBATEK) Execution Time: nS+1N+1I (POP), (n+1)S+2N+1I (POP PC), or (n-1)S+2N (PUSH).
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let is_load = insn.is_load();
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let rb = insn.rb();
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let mut pipeline_action = CpuPipelineAction::IncPC;
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let mut addr = self.gpr[rb];
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let rlist = insn.register_list();
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if is_load {
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for r in rlist {
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let val = self.load_32(addr, bus);
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addr += 4;
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self.add_cycle();
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self.set_reg(r, val);
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}
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} else {
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for r in rlist.into_iter().rev() {
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self.store_32(addr, self.gpr[r], bus);
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addr += 4;
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}
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}
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Ok(pipeline_action)
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}
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fn exec_thumb_branch_with_cond(
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&mut self,
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_bus: &mut Bus,
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@ -329,11 +411,14 @@ impl Core {
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ThumbFormat::HiRegOpOrBranchExchange => self.exec_thumb_hi_reg_op_or_bx(bus, insn),
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ThumbFormat::LdrPc => self.exec_thumb_ldr_pc(bus, insn),
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ThumbFormat::LdrStrRegOffset => self.exec_thumb_ldr_str_reg_offset(bus, insn),
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ThumbFormat::LdrStrSHB => self.exec_thumb_ldr_str_shb(bus, insn),
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ThumbFormat::LdrStrImmOffset => self.exec_thumb_ldr_str_imm_offset(bus, insn),
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ThumbFormat::LdrStrHalfWord => self.exec_thumb_ldr_str_halfword(bus, insn),
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ThumbFormat::LdrStrSp => self.exec_thumb_ldr_str_sp(bus, insn),
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ThumbFormat::LdrAddress => self.exec_thumb_ldr_address(bus, insn),
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ThumbFormat::AddSp => self.exec_thumb_add_sp(bus, insn),
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ThumbFormat::PushPop => self.exec_thumb_push_pop(bus, insn),
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ThumbFormat::LdmStm => self.exec_thumb_ldm_stm(bus, insn),
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ThumbFormat::BranchConditional => self.exec_thumb_branch_with_cond(bus, insn),
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ThumbFormat::Branch => self.exec_thumb_branch(bus, insn),
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ThumbFormat::BranchLongWithLink => self.exec_thumb_branch_long_with_link(bus, insn),
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@ -199,6 +199,9 @@ impl ThumbInstruction {
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const FLAG_R: usize = 8;
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const FLAG_S: usize = 7;
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const FLAG_LOW_OFFSET: usize = 11;
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const FLAG_SP: usize = 11;
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const FLAG_SIGN_EXTEND: usize = 10;
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const FLAG_HALFWORD: usize = 11;
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pub fn rd(&self) -> usize {
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match self.fmt {
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@ -265,7 +268,7 @@ impl ThumbInstruction {
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match self.fmt {
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ThumbFormat::LdrStrRegOffset => self.raw.bit(10),
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ThumbFormat::LdrStrImmOffset => self.raw.bit(12),
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_ => unreachable!()
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_ => unreachable!(),
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}
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}
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@ -314,6 +317,11 @@ impl ThumbInstruction {
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/// All instructions constants were generated using an ARM assembler.
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mod tests {
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use super::*;
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use crate::arm7tdmi::{
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cpu::{Core, CpuPipelineAction},
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Bus,
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};
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use crate::sysbus::BoxedMemory;
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#[test]
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fn mov_low_reg() {
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@ -336,11 +344,14 @@ mod tests {
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assert_eq!(core.get_reg(0), 0x27);
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}
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// #[test]
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// fn decode_add_sub() {
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// let insn = ThumbInstruction::decode(0xac19, 0).unwrap();
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// assert!(format!("add\tr4, r4"))
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// }
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#[test]
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fn ldr_pc() {
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use crate::arm7tdmi::cpu::{Core, CpuPipelineAction};
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use crate::sysbus::BoxedMemory;
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// ldr r0, [pc, #4]
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let insn = ThumbInstruction::decode(0x4801, 0x6).unwrap();
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@ -363,12 +374,6 @@ mod tests {
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#[test]
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fn ldr_str_reg_offset() {
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use crate::arm7tdmi::{
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cpu::{Core, CpuPipelineAction},
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Bus,
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};
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use crate::sysbus::BoxedMemory;
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// str r0, [r4, r1]
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||||
let str_insn = ThumbInstruction::decode(0x5060, 0x6).unwrap();
|
||||
// ldrb r2, [r4, r1]
|
||||
|
|
@ -400,4 +405,44 @@ mod tests {
|
|||
);
|
||||
assert_eq!(core.get_reg(2), 0x78);
|
||||
}
|
||||
|
||||
#[allow(overflowing_literals)]
|
||||
#[test]
|
||||
fn format8() {
|
||||
let mut core = Core::new();
|
||||
let bytes = vec![
|
||||
/* 0: */ 0xaa, 0xbb, 0xcc, 0xdd, 0xaa, 0xbb, 0xcc, 0xdd,
|
||||
/* 8: */ 0xaa, 0xbb, 0xcc, 0xdd, 0xaa, 0xbb, 0xcc, 0xdd,
|
||||
/* 10: */ 0xaa, 0xbb, 0xcc, 0xdd, 0xaa, 0xbb, 0xcc, 0xdd,
|
||||
];
|
||||
let mut mem = BoxedMemory::new(bytes.into_boxed_slice());
|
||||
|
||||
|
||||
core.gpr[4] = 0x12345678;
|
||||
core.gpr[3] = 0x2;
|
||||
core.gpr[0] = 0x4;
|
||||
// strh r4, [r3, r0]
|
||||
let decoded = ThumbInstruction::decode(0x521c, 0).unwrap();
|
||||
assert_eq!(format!("{}", decoded), "strh\tr4, [r3, r0]");
|
||||
core.exec_thumb(&mut mem, decoded).unwrap();
|
||||
assert_eq!(&mem.get_bytes(0x6)[..4], [0x78, 0x56, 0xaa, 0xbb]);
|
||||
|
||||
// ldsb r2, [r7, r1]
|
||||
core.gpr[2] = 0;
|
||||
core.gpr[7] = 0x10;
|
||||
core.gpr[1] = 0x5;
|
||||
let decoded = ThumbInstruction::decode(0x567a, 0).unwrap();
|
||||
assert_eq!(format!("{}", decoded), "ldsb\tr2, [r7, r1]");
|
||||
core.exec_thumb(&mut mem, decoded).unwrap();
|
||||
assert_eq!(core.gpr[2], mem.read_8(0x15) as i8 as u32);
|
||||
|
||||
// ldsh r3, [r4, r2]
|
||||
core.gpr[3] = 0x0;
|
||||
core.gpr[4] = 0x0;
|
||||
core.gpr[2] = 0x6;
|
||||
let decoded = ThumbInstruction::decode(0x5ea3, 0).unwrap();
|
||||
assert_eq!(format!("{}", decoded), "ldsh\tr3, [r4, r2]");
|
||||
core.exec_thumb(&mut mem, decoded).unwrap();
|
||||
assert_eq!(core.gpr[3], 0x5678);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@ use crate::arm7tdmi::{Addr, CpuState};
|
|||
use crate::disass::Disassembler;
|
||||
use crate::GBAError;
|
||||
|
||||
use super::{parser::Value, Debugger, DebuggerError, DebuggerResult};
|
||||
use super::palette_view::create_palette_view;
|
||||
use super::{parser::Value, Debugger, DebuggerError, DebuggerResult};
|
||||
|
||||
use ansi_term::Colour;
|
||||
|
||||
|
|
@ -80,19 +80,19 @@ impl Command {
|
|||
break;
|
||||
}
|
||||
match debugger.gba.step() {
|
||||
Ok(insn) => {
|
||||
println!(
|
||||
"@0x{:08x}:\t{}",
|
||||
insn.get_pc(),
|
||||
Colour::Yellow.italic().paint(format!("{} ", insn))
|
||||
);
|
||||
}
|
||||
// Ok(insn) => {
|
||||
// println!(
|
||||
// "@0x{:08x}:\t{}",
|
||||
// insn.get_pc(),
|
||||
// Colour::Yellow.italic().paint(format!("{} ", insn))
|
||||
// );
|
||||
// }
|
||||
Err(GBAError::CpuError(e)) => {
|
||||
println!("{}: {}", "cpu encountered an error".red(), e);
|
||||
println!("cpu: {:x?}", debugger.gba.cpu);
|
||||
break;
|
||||
}
|
||||
_ => unreachable!(),
|
||||
_ => (),
|
||||
};
|
||||
},
|
||||
HexDump(addr, nbytes) => {
|
||||
|
|
|
|||
|
|
@ -43,7 +43,6 @@ impl ColoredRect {
|
|||
}
|
||||
|
||||
pub fn create_palette_view(palette_ram: &[u8]) {
|
||||
|
||||
let palette = Palette::from(palette_ram);
|
||||
|
||||
let sdl_context = sdl2::init().unwrap();
|
||||
|
|
|
|||
Reference in a new issue