Implement DMA, WIP
I have fought very hard against the rust ownership model, In the end for DMA to play nice with my code, I had to resort to use unsafe code for now.. The DMA implementation itself is not accurate to say the least, but will have to do for now. Tonc's dma_demo.gba plays but with a visual glitch. Former-commit-id: 3b9cdcb2d09c78701290f2c48b77f9f3487e85c9
This commit is contained in:
Michel Heily
parent
3a1d5c10ce
commit
c78a111ad4
264
src/core/dma.rs
264
src/core/dma.rs
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@ -1,74 +1,210 @@
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// use super::arm7tdmi::{Addr, Bus};
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// use super::ioregs::consts::*;
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// use super::sysbus::SysBus;
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// use super::{EmuIoDev, Interrupt};
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use std::collections::VecDeque;
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// #[allow(non_camel_case_types)]
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// #[derive(Debug)]
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// pub struct DmaChannel {
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// src_ioreg: Addr, /* Source Address register */
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// dst_ioreg: Addr, /* Destination Address register */
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// wc_ioreg: Addr, /* Word Count 14bit */
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// }
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use super::arm7tdmi::{Addr, Bus};
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use super::sysbus::SysBus;
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use super::{Interrupt, IrqBitmask, SyncedIoDevice};
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// #[derive(Debug, Primitive)]
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// enum DmaAddrControl {
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// Increment = 0,
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// Decrement = 1,
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// Fixed = 2,
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// IncrementReloadProhibited = 3,
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// }
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use num::FromPrimitive;
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// #[derive(Debug)]
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// enum DmaTransferType {
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// Xfer16bit,
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// Xfer32bit,
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// }
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#[derive(Debug)]
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enum DmaTransferType {
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Xfer16bit,
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Xfer32bit,
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}
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// #[derive(Debug, Primitive)]
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// enum DmaStartTiming {
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// Immediately = 0,
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// VBlank = 1,
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// HBlank = 2,
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// Special = 3,
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// }
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#[derive(Debug)]
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pub struct DmaChannel {
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id: usize,
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// #[derive(Debug)]
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// struct DmaControl {
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// dst_addr_ctl: DmaAddrControl,
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// src_addr_ctl: DmaAddrControl,
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// repeat: bool,
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// xfer: DmaTransferType,
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// start_timing: DmaStartTiming,
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// irq_upon_end_of_wc: bool,
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// enable: bool,
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// }
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pub src: u32,
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pub dst: u32,
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pub wc: u32,
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pub ctrl: DmaChannelCtrl,
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// impl DmaChannel {
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// pub fn new(src_ioreg: Addr, dst_ioreg: Addr, wc_ioreg: Addr) -> DmaChannel {
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// DmaChannel {
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// src_ioreg,
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// dst_ioreg,
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// wc_ioreg,
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// }
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// }
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running: bool,
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cycles: usize,
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start_cycles: usize,
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irq: Interrupt,
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}
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// // fn src_addr(&self, sysbus: &SysBus) -> Addr {
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// // sysbus.ioregs.read_32(self.src_ioreg - IO_BASE) as Addr
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// // }
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impl DmaChannel {
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pub fn new(id: usize) -> DmaChannel {
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if id > 3 {
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panic!("invalid dma id {}", id);
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}
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DmaChannel {
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id: id,
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irq: Interrupt::from_usize(id + 8).unwrap(),
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running: false,
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src: 0,
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dst: 0,
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wc: 0,
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ctrl: DmaChannelCtrl(0),
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cycles: 0,
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start_cycles: 0,
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}
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}
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// // fn dst_addr(&self, sysbus: &SysBus) -> Addr {
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// // sysbus.ioregs.read_32(self.dst_ioreg - IO_BASE) as Addr
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// // }
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pub fn is_running(&self) -> bool {
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self.running
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}
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// // fn word_count(&self, sysbus: &SysBus) -> usize {
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// // sysbus.ioregs.read_reg(self.wc_ioreg) as usize
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// // }
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// }
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pub fn write_src_low(&mut self, low: u16) {
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let src = self.src;
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self.src = (src & 0xffff0000) | (low as u32);
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}
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// impl EmuIoDev for DmaChannel {
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// fn step(&mut self, cycles: usize, sysbus: &mut SysBus) -> (usize, Option<Interrupt>) {
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// // TODO
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// (0, None)
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// }
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// }
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pub fn write_src_high(&mut self, high: u16) {
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let src = self.src;
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let high = high as u32;
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self.src = (src & 0xffff) | (high << 16);
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}
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pub fn write_dst_low(&mut self, low: u16) {
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let dst = self.dst;
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self.dst = (dst & 0xffff0000) | (low as u32);
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}
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pub fn write_dst_high(&mut self, high: u16) {
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let dst = self.dst;
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let high = high as u32;
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self.dst = (dst & 0xffff) | (high << 16);
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}
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pub fn write_word_count(&mut self, value: u16) {
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self.wc = value as u32;
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}
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pub fn write_dma_ctrl(&mut self, value: u16) -> bool {
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let ctrl = DmaChannelCtrl(value);
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let mut start_immediately = false;
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if ctrl.is_enabled() {
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self.start_cycles = self.cycles;
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self.running = true;
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if ctrl.timing() == 0 {
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start_immediately = true;
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}
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}
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self.ctrl = ctrl;
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return start_immediately;
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}
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fn xfer(&mut self, sb: &mut SysBus, irqs: &mut IrqBitmask) {
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let word_size = if self.ctrl.is_32bit() { 4 } else { 2 };
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let dst_rld = self.dst;
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for word in 0..self.wc {
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if word_size == 4 {
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let w = sb.read_32(self.src);
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sb.write_32(self.dst, w)
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} else {
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let hw = sb.read_16(self.src);
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// println!("src {:x} dst {:x}", self.src, self.dst);
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sb.write_16(self.dst, hw)
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}
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match self.ctrl.src_adj() {
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/* Increment */ 0 => self.src += word_size,
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/* Decrement */ 1 => self.src -= word_size,
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/* Fixed */ 2 => {}
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_ => panic!("forbidden DMA source address adjustment"),
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}
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match self.ctrl.dst_adj() {
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/* Increment[+Reload] */ 0 | 3 => self.dst += word_size,
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/* Decrement */ 1 => self.dst -= word_size,
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/* Fixed */ 2 => {}
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_ => panic!("forbidden DMA dest address adjustment"),
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}
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}
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if self.ctrl.is_triggering_irq() {
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irqs.add_irq(self.irq);
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}
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if self.ctrl.repeat() {
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self.start_cycles = self.cycles;
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/* reload */
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if 3 == self.ctrl.dst_adj() {
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self.dst = dst_rld;
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}
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} else {
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self.running = false;
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self.ctrl.set_enabled(false);
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}
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}
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}
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#[derive(Debug)]
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pub struct DmaController {
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pub channels: [DmaChannel; 4],
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xfers_queue: VecDeque<usize>,
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cycles: usize,
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}
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impl DmaController {
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pub fn new() -> DmaController {
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DmaController {
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channels: [
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DmaChannel::new(0),
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DmaChannel::new(1),
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DmaChannel::new(2),
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DmaChannel::new(3),
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],
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xfers_queue: VecDeque::new(),
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cycles: 0,
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}
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}
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pub fn perform_work(&mut self, sb: &mut SysBus, irqs: &mut IrqBitmask) -> bool {
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if self.xfers_queue.is_empty() {
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false
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} else {
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while let Some(id) = self.xfers_queue.pop_front() {
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self.channels[id].xfer(sb, irqs)
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}
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true
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}
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}
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pub fn write_16(&mut self, channel_id: usize, ofs: u32, value: u16) {
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match ofs {
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0 => self.channels[channel_id].write_src_low(value),
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2 => self.channels[channel_id].write_src_high(value),
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4 => self.channels[channel_id].write_dst_low(value),
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6 => self.channels[channel_id].write_dst_high(value),
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8 => self.channels[channel_id].write_word_count(value),
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10 => {
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if self.channels[channel_id].write_dma_ctrl(value) {
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self.xfers_queue.push_back(channel_id)
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}
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}
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_ => panic!("Invalid dma offset"),
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}
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}
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pub fn notify_vblank(&mut self) {
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for i in 0..4 {
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if self.channels[i].ctrl.is_enabled() && self.channels[i].ctrl.timing() == 1 {
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self.xfers_queue.push_back(i);
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}
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}
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}
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pub fn notify_hblank(&mut self) {
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for i in 0..4 {
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if self.channels[i].ctrl.is_enabled() && self.channels[i].ctrl.timing() == 2 {
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self.xfers_queue.push_back(i);
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}
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}
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}
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}
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bitfield! {
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#[derive(Default)]
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pub struct DmaChannelCtrl(u16);
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impl Debug;
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u16;
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dst_adj, _ : 6, 5;
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src_adj, _ : 8, 7;
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repeat, _ : 9;
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is_32bit, _: 10;
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timing, _: 13, 12;
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is_triggering_irq, _: 14;
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is_enabled, set_enabled: 15;
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}
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103
src/core/gba.rs
103
src/core/gba.rs
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@ -1,42 +1,19 @@
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/// Struct containing everything
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///
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use std::cell::RefCell;
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use std::rc::Rc;
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use super::arm7tdmi::{exception::Exception, Core, DecodedInstruction};
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use super::cartridge::Cartridge;
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use super::gpu::*;
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use super::interrupt::*;
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use super::ioregs::IoRegs;
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use super::iodev::*;
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use super::sysbus::SysBus;
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use super::timer::Timers;
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use super::GBAResult;
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use super::SyncedIoDevice;
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use crate::backend::*;
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#[derive(Debug)]
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pub struct IoDevices {
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pub intc: InterruptController,
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pub gpu: Gpu,
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pub timers: Timers,
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}
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impl IoDevices {
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pub fn new() -> IoDevices {
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IoDevices {
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intc: InterruptController::new(),
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gpu: Gpu::new(),
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timers: Timers::new(),
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}
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}
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}
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pub struct GameBoyAdvance {
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backend: Box<EmulatorBackend>,
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backend: Box<dyn EmulatorBackend>,
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pub cpu: Core,
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pub sysbus: SysBus,
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pub io: Rc<RefCell<IoDevices>>,
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pub sysbus: Box<SysBus>,
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}
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impl GameBoyAdvance {
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@ -44,51 +21,63 @@ impl GameBoyAdvance {
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cpu: Core,
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bios_rom: Vec<u8>,
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gamepak: Cartridge,
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backend: Box<EmulatorBackend>,
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backend: Box<dyn EmulatorBackend>,
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) -> GameBoyAdvance {
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let io = Rc::new(RefCell::new(IoDevices::new()));
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let ioregs = IoRegs::new(io.clone());
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let sysbus = SysBus::new(io.clone(), bios_rom, gamepak, ioregs);
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let io = IoDevices::new();
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GameBoyAdvance {
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backend: backend,
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cpu: cpu,
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sysbus: sysbus,
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io: io.clone(),
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sysbus: Box::new(SysBus::new(io, bios_rom, gamepak)),
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}
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}
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pub fn frame(&mut self) {
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self.update_key_state();
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while self.io.borrow().gpu.state != GpuState::VBlank {
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let cycles = self.emulate_cpu();
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self.emulate_peripherals(cycles);
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while self.sysbus.io.gpu.state != GpuState::VBlank {
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self.step_new();
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}
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self.backend.render(self.io.borrow().gpu.get_framebuffer());
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while self.io.borrow().gpu.state == GpuState::VBlank {
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let cycles = self.emulate_cpu();
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self.emulate_peripherals(cycles);
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self.backend.render(self.sysbus.io.gpu.get_framebuffer());
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while self.sysbus.io.gpu.state == GpuState::VBlank {
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self.step_new();
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}
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}
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fn update_key_state(&mut self) {
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self.sysbus.ioregs.keyinput = self.backend.get_key_state();
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self.sysbus.io.keyinput = self.backend.get_key_state();
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}
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pub fn emulate_cpu(&mut self) -> usize {
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// TODO deprecate
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pub fn step(&mut self) -> GBAResult<DecodedInstruction> {
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let previous_cycles = self.cpu.cycles;
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self.cpu.step(&mut self.sysbus).unwrap();
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self.cpu.cycles - previous_cycles
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let executed_insn = self.cpu.step_one(&mut self.sysbus)?;
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let cycles = self.cpu.cycles - previous_cycles;
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Ok(executed_insn)
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}
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pub fn emulate_peripherals(&mut self, cycles: usize) {
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pub fn step_new(&mut self) {
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let mut irqs = IrqBitmask(0);
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let mut io = self.io.borrow_mut();
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let previous_cycles = self.cpu.cycles;
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// // I hate myself for doing this, but rust left me no choice.
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let io = unsafe {
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let ptr = &mut *self.sysbus as *mut SysBus;
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&mut (*ptr).io as &mut IoDevices
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};
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if !io.dmac.perform_work(&mut self.sysbus, &mut irqs) {
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self.cpu.step(&mut self.sysbus).unwrap();
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}
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let cycles = self.cpu.cycles - previous_cycles;
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io.timers.step(cycles, &mut self.sysbus, &mut irqs);
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io.gpu.step(cycles, &mut self.sysbus, &mut irqs);
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if let Some(new_gpu_state) = io.gpu.step(cycles, &mut self.sysbus, &mut irqs) {
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match new_gpu_state {
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GpuState::VBlank => io.dmac.notify_vblank(),
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GpuState::HBlank => io.dmac.notify_hblank(),
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_ => {}
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}
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}
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if !self.cpu.cpsr.irq_disabled() {
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io.intc.request_irqs(irqs);
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@ -97,18 +86,4 @@ impl GameBoyAdvance {
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}
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}
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}
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pub fn step(&mut self) -> GBAResult<DecodedInstruction> {
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let previous_cycles = self.cpu.cycles;
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let executed_insn = self.cpu.step_one(&mut self.sysbus)?;
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let cycles = self.cpu.cycles - previous_cycles;
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self.emulate_peripherals(cycles);
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if self.io.borrow().gpu.state == GpuState::VBlank {
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self.backend.render(self.io.borrow().gpu.get_framebuffer());
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}
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Ok(executed_insn)
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}
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}
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@ -361,7 +361,7 @@ impl Gpu {
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}
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fn scanline_aff_bg(&mut self, bg: usize, sb: &mut SysBus) {
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// TODO
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// TODO
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}
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fn scanline_mode3(&mut self, bg: usize, sb: &mut SysBus) {
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@ -444,10 +444,14 @@ impl Gpu {
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pub fn get_framebuffer(&self) -> &[u32] {
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&self.frame_buffer.0
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}
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}
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impl SyncedIoDevice for Gpu {
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fn step(&mut self, cycles: usize, sb: &mut SysBus, irqs: &mut IrqBitmask) {
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// Returns the new gpu state
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pub fn step(
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&mut self,
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cycles: usize,
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sb: &mut SysBus,
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irqs: &mut IrqBitmask,
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) -> Option<GpuState> {
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self.cycles += cycles;
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if self.dispstat.vcount_setting() != 0 {
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@ -472,12 +476,14 @@ impl SyncedIoDevice for Gpu {
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irqs.set_LCD_HBlank(true);
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};
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self.state = HBlank;
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return Some(HBlank);
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} else {
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self.dispstat.set_vblank(true);
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if self.dispstat.vblank_irq_enable() {
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irqs.set_LCD_VBlank(true);
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};
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self.state = VBlank;
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return Some(VBlank);
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};
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}
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}
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@ -487,6 +493,7 @@ impl SyncedIoDevice for Gpu {
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self.state = HDraw;
|
||||
self.dispstat.set_hblank(false);
|
||||
self.dispstat.set_vblank(false);
|
||||
return Some(HDraw);
|
||||
}
|
||||
}
|
||||
VBlank => {
|
||||
|
|
@ -497,9 +504,12 @@ impl SyncedIoDevice for Gpu {
|
|||
self.dispstat.set_vblank(false);
|
||||
self.current_scanline = 0;
|
||||
self.render_scanline(sb);
|
||||
return Some(HDraw);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return None;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,28 +1,35 @@
|
|||
use std::cell::RefCell;
|
||||
use std::rc::Rc;
|
||||
|
||||
use super::arm7tdmi::{Addr, Bus};
|
||||
use super::gba::IoDevices;
|
||||
use super::dma::DmaController;
|
||||
use super::gpu::regs::WindowFlags;
|
||||
use super::gpu::*;
|
||||
use super::interrupt::InterruptController;
|
||||
use super::keypad;
|
||||
use super::sysbus::BoxedMemory;
|
||||
use super::timer::Timers;
|
||||
|
||||
use consts::*;
|
||||
|
||||
#[derive(Debug)]
|
||||
pub struct IoRegs {
|
||||
mem: BoxedMemory,
|
||||
pub io: Rc<RefCell<IoDevices>>,
|
||||
pub struct IoDevices {
|
||||
pub intc: InterruptController,
|
||||
pub gpu: Gpu,
|
||||
pub timers: Timers,
|
||||
pub dmac: DmaController,
|
||||
pub keyinput: u16,
|
||||
pub post_boot_flag: bool,
|
||||
pub waitcnt: WaitControl, // TODO also implement 4000800
|
||||
|
||||
mem: BoxedMemory,
|
||||
}
|
||||
|
||||
impl IoRegs {
|
||||
pub fn new(io: Rc<RefCell<IoDevices>>) -> IoRegs {
|
||||
IoRegs {
|
||||
impl IoDevices {
|
||||
pub fn new() -> IoDevices {
|
||||
IoDevices {
|
||||
gpu: Gpu::new(),
|
||||
timers: Timers::new(),
|
||||
dmac: DmaController::new(),
|
||||
intc: InterruptController::new(),
|
||||
mem: BoxedMemory::new(vec![0; 0x800].into_boxed_slice()),
|
||||
io: io,
|
||||
post_boot_flag: false,
|
||||
keyinput: keypad::KEYINPUT_ALL_RELEASED,
|
||||
waitcnt: WaitControl(0),
|
||||
|
|
@ -30,14 +37,15 @@ impl IoRegs {
|
|||
}
|
||||
}
|
||||
|
||||
impl Bus for IoRegs {
|
||||
impl Bus for IoDevices {
|
||||
fn read_32(&self, addr: Addr) -> u32 {
|
||||
(self.read_16(addr + 2) as u32) << 16 | (self.read_16(addr) as u32)
|
||||
}
|
||||
|
||||
fn read_16(&self, addr: Addr) -> u16 {
|
||||
let io = self.io.borrow();
|
||||
match addr + IO_BASE {
|
||||
let io = self;
|
||||
let io_addr = addr + IO_BASE;
|
||||
match io_addr {
|
||||
REG_DISPCNT => io.gpu.dispcnt.0,
|
||||
REG_DISPSTAT => io.gpu.dispstat.0,
|
||||
REG_VCOUNT => io.gpu.current_scanline as u16,
|
||||
|
|
@ -71,12 +79,24 @@ impl Bus for IoRegs {
|
|||
REG_TM3CNT_L => io.timers[3].timer_data,
|
||||
REG_TM3CNT_H => io.timers[3].timer_ctl.0,
|
||||
|
||||
REG_WAITCNT => self.waitcnt.0,
|
||||
REG_DMA0CNT_H => io.dmac.channels[0].ctrl.0,
|
||||
REG_DMA1CNT_H => io.dmac.channels[1].ctrl.0,
|
||||
REG_DMA2CNT_H => io.dmac.channels[2].ctrl.0,
|
||||
REG_DMA3CNT_H => io.dmac.channels[3].ctrl.0,
|
||||
|
||||
REG_POSTFLG => self.post_boot_flag as u16,
|
||||
REG_WAITCNT => io.waitcnt.0,
|
||||
|
||||
REG_POSTFLG => io.post_boot_flag as u16,
|
||||
REG_HALTCNT => 0,
|
||||
REG_KEYINPUT => self.keyinput as u16,
|
||||
_ => self.mem.read_16(addr),
|
||||
REG_KEYINPUT => io.keyinput as u16,
|
||||
_ => {
|
||||
println!(
|
||||
"Unimplemented read from {:x} {}",
|
||||
io_addr,
|
||||
io_reg_string(io_addr)
|
||||
);
|
||||
io.mem.read_16(addr)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -95,8 +115,10 @@ impl Bus for IoRegs {
|
|||
}
|
||||
|
||||
fn write_16(&mut self, addr: Addr, value: u16) {
|
||||
let mut io = self.io.borrow_mut();
|
||||
match addr + IO_BASE {
|
||||
let mut io = self;
|
||||
io.mem.write_16(addr, value);
|
||||
let io_addr = addr + IO_BASE;
|
||||
match io_addr {
|
||||
REG_DISPCNT => io.gpu.dispcnt.0 = value,
|
||||
REG_DISPSTAT => io.gpu.dispstat.0 |= value & !3,
|
||||
REG_BG0CNT => io.gpu.bg[0].bgcnt.0 = value,
|
||||
|
|
@ -192,18 +214,22 @@ impl Bus for IoRegs {
|
|||
}
|
||||
REG_TM3CNT_H => io.timers[3].timer_ctl.0 = value,
|
||||
|
||||
REG_WAITCNT => self.waitcnt.0 = value,
|
||||
DMA_BASE..=REG_DMA3CNT_H => {
|
||||
let ofs = io_addr - DMA_BASE;
|
||||
let channel_id = (ofs / 12) as usize;
|
||||
io.dmac.write_16(channel_id, ofs % 12, value)
|
||||
}
|
||||
|
||||
REG_POSTFLG => self.post_boot_flag = value != 0,
|
||||
REG_WAITCNT => io.waitcnt.0 = value,
|
||||
|
||||
REG_POSTFLG => io.post_boot_flag = value != 0,
|
||||
REG_HALTCNT => {}
|
||||
_ => {
|
||||
let ioreg_addr = IO_BASE + addr;
|
||||
println!(
|
||||
"Unimplemented write to {:x} {}",
|
||||
ioreg_addr,
|
||||
io_reg_string(ioreg_addr)
|
||||
io_addr,
|
||||
io_reg_string(io_addr)
|
||||
);
|
||||
self.mem.write_16(addr, value);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -301,6 +327,7 @@ pub mod consts {
|
|||
pub const REG_WAVE_RAM: Addr = 0x0400_0090; // Channel 3 Wave Pattern RAM (2 banks!!)
|
||||
pub const REG_FIFO_A: Addr = 0x0400_00A0; // 4 W Channel A FIFO, Data 0-3
|
||||
pub const REG_FIFO_B: Addr = 0x0400_00A4; // 4 W Channel B FIFO, Data 0-3
|
||||
pub const DMA_BASE: Addr = REG_DMA0SAD;
|
||||
pub const REG_DMA0SAD: Addr = 0x0400_00B0; // 4 W DMA 0 Source Address
|
||||
pub const REG_DMA0DAD: Addr = 0x0400_00B4; // 4 W DMA 0 Destination Address
|
||||
pub const REG_DMA0CNT_L: Addr = 0x0400_00B8; // 2 W DMA 0 Word Count
|
||||
|
|
@ -4,7 +4,7 @@ pub mod gpu;
|
|||
pub mod sysbus;
|
||||
pub use sysbus::SysBus;
|
||||
pub mod interrupt;
|
||||
pub mod ioregs;
|
||||
pub mod iodev;
|
||||
pub use interrupt::Interrupt;
|
||||
pub use interrupt::IrqBitmask;
|
||||
pub mod gba;
|
||||
|
|
|
|||
|
|
@ -1,15 +1,13 @@
|
|||
use std::cell::RefCell;
|
||||
use std::fmt;
|
||||
use std::ops::Add;
|
||||
use std::rc::Rc;
|
||||
|
||||
use byteorder::{LittleEndian, ReadBytesExt, WriteBytesExt};
|
||||
|
||||
use super::arm7tdmi::bus::Bus;
|
||||
use super::arm7tdmi::Addr;
|
||||
use super::gba::IoDevices;
|
||||
use super::cartridge::Cartridge;
|
||||
use super::gpu::GpuState;
|
||||
use super::{cartridge::Cartridge, ioregs::IoRegs};
|
||||
use super::iodev::IoDevices;
|
||||
|
||||
const VIDEO_RAM_SIZE: usize = 128 * 1024;
|
||||
const WORK_RAM_SIZE: usize = 256 * 1024;
|
||||
|
|
@ -141,13 +139,11 @@ impl Bus for DummyBus {
|
|||
|
||||
#[derive(Debug)]
|
||||
pub struct SysBus {
|
||||
pub io: Rc<RefCell<IoDevices>>,
|
||||
pub io: IoDevices,
|
||||
|
||||
bios: BoxedMemory,
|
||||
onboard_work_ram: BoxedMemory,
|
||||
internal_work_ram: BoxedMemory,
|
||||
/// Currently model the IOMem as regular buffer, later make it into something more sophisticated.
|
||||
pub ioregs: IoRegs,
|
||||
pub palette_ram: BoxedMemory,
|
||||
pub vram: BoxedMemory,
|
||||
pub oam: BoxedMemory,
|
||||
|
|
@ -156,19 +152,13 @@ pub struct SysBus {
|
|||
}
|
||||
|
||||
impl SysBus {
|
||||
pub fn new(
|
||||
io: Rc<RefCell<IoDevices>>,
|
||||
bios_rom: Vec<u8>,
|
||||
gamepak: Cartridge,
|
||||
ioregs: IoRegs,
|
||||
) -> SysBus {
|
||||
pub fn new(io: IoDevices, bios_rom: Vec<u8>, gamepak: Cartridge) -> SysBus {
|
||||
SysBus {
|
||||
io: io,
|
||||
|
||||
bios: BoxedMemory::new(bios_rom.into_boxed_slice()),
|
||||
onboard_work_ram: BoxedMemory::new(vec![0; WORK_RAM_SIZE].into_boxed_slice()),
|
||||
internal_work_ram: BoxedMemory::new(vec![0; INTERNAL_RAM_SIZE].into_boxed_slice()),
|
||||
ioregs: ioregs,
|
||||
palette_ram: BoxedMemory::new(vec![0; PALETTE_RAM_SIZE].into_boxed_slice()),
|
||||
vram: BoxedMemory::new(vec![0; VIDEO_RAM_SIZE].into_boxed_slice()),
|
||||
oam: BoxedMemory::new(vec![0; OAM_SIZE].into_boxed_slice()),
|
||||
|
|
@ -177,13 +167,13 @@ impl SysBus {
|
|||
}
|
||||
}
|
||||
|
||||
fn map(&self, addr: Addr) -> (&Bus, Addr) {
|
||||
fn map(&self, addr: Addr) -> (&dyn Bus, Addr) {
|
||||
let ofs = addr & 0x00ff_ffff;
|
||||
match addr & 0xff000000 {
|
||||
BIOS_ADDR => (&self.bios, ofs),
|
||||
EWRAM_ADDR => (&self.onboard_work_ram, ofs & 0x3_ffff),
|
||||
IWRAM_ADDR => (&self.internal_work_ram, ofs & 0x7fff),
|
||||
IOMEM_ADDR => (&self.ioregs, {
|
||||
IOMEM_ADDR => (&self.io, {
|
||||
if ofs & 0xffff == 0x8000 {
|
||||
0x800
|
||||
} else {
|
||||
|
|
@ -205,13 +195,13 @@ impl SysBus {
|
|||
}
|
||||
|
||||
/// TODO proc-macro for generating this function
|
||||
fn map_mut(&mut self, addr: Addr) -> (&mut Bus, Addr) {
|
||||
fn map_mut(&mut self, addr: Addr) -> (&mut dyn Bus, Addr) {
|
||||
let ofs = addr & 0x00ff_ffff;
|
||||
match addr & 0xff000000 {
|
||||
BIOS_ADDR => (&mut self.bios, ofs),
|
||||
EWRAM_ADDR => (&mut self.onboard_work_ram, ofs & 0x3_ffff),
|
||||
IWRAM_ADDR => (&mut self.internal_work_ram, ofs & 0x7fff),
|
||||
IOMEM_ADDR => (&mut self.ioregs, {
|
||||
IOMEM_ADDR => (&mut self.io, {
|
||||
if ofs & 0xffff == 0x8000 {
|
||||
0x800
|
||||
} else {
|
||||
|
|
@ -249,24 +239,24 @@ impl SysBus {
|
|||
MemoryAccessWidth::MemoryAccess32 => cycles += 2,
|
||||
_ => cycles += 1,
|
||||
}
|
||||
if self.io.borrow().gpu.state == GpuState::HDraw {
|
||||
if self.io.gpu.state == GpuState::HDraw {
|
||||
cycles += 1;
|
||||
}
|
||||
}
|
||||
GAMEPAK_WS0_ADDR => match access.0 {
|
||||
MemoryAccessType::NonSeq => match access.1 {
|
||||
MemoryAccessWidth::MemoryAccess32 => {
|
||||
cycles += nonseq_cycles[self.ioregs.waitcnt.ws0_first_access() as usize];
|
||||
cycles += seq_cycles[self.ioregs.waitcnt.ws0_second_access() as usize];
|
||||
cycles += nonseq_cycles[self.io.waitcnt.ws0_first_access() as usize];
|
||||
cycles += seq_cycles[self.io.waitcnt.ws0_second_access() as usize];
|
||||
}
|
||||
_ => {
|
||||
cycles += nonseq_cycles[self.ioregs.waitcnt.ws0_first_access() as usize];
|
||||
cycles += nonseq_cycles[self.io.waitcnt.ws0_first_access() as usize];
|
||||
}
|
||||
},
|
||||
MemoryAccessType::Seq => {
|
||||
cycles += seq_cycles[self.ioregs.waitcnt.ws0_second_access() as usize];
|
||||
cycles += seq_cycles[self.io.waitcnt.ws0_second_access() as usize];
|
||||
if access.1 == MemoryAccessWidth::MemoryAccess32 {
|
||||
cycles += seq_cycles[self.ioregs.waitcnt.ws0_second_access() as usize];
|
||||
cycles += seq_cycles[self.io.waitcnt.ws0_second_access() as usize];
|
||||
}
|
||||
}
|
||||
},
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ use crate::core::GBAError;
|
|||
use crate::disass::Disassembler;
|
||||
|
||||
use super::palette_view::create_palette_view;
|
||||
use super::tile_view::create_tile_view;
|
||||
// use super::tile_view::create_tile_view;
|
||||
use super::{parser::Value, Debugger, DebuggerError, DebuggerResult};
|
||||
|
||||
use ansi_term::Colour;
|
||||
|
|
@ -32,7 +32,7 @@ pub enum Command {
|
|||
AddBreakpoint(Addr),
|
||||
DelBreakpoint(Addr),
|
||||
PaletteView,
|
||||
TileView(u32),
|
||||
// TileView(u32),
|
||||
ClearBreakpoints,
|
||||
ListBreakpoints,
|
||||
Reset,
|
||||
|
|
@ -44,7 +44,7 @@ impl Command {
|
|||
use Command::*;
|
||||
match *self {
|
||||
Info => println!("{}", debugger.gba.cpu),
|
||||
DisplayInfo => println!("GPU: {:#?}", debugger.gba.io.borrow().gpu),
|
||||
DisplayInfo => { /*println!("GPU: {:#?}", debugger.gba.sysbus.io.gpu)*/ }
|
||||
Step(count) => {
|
||||
for _ in 0..count {
|
||||
match debugger.gba.step() {
|
||||
|
|
@ -154,7 +154,7 @@ impl Command {
|
|||
}
|
||||
}
|
||||
PaletteView => create_palette_view(&debugger.gba.sysbus.palette_ram.mem),
|
||||
TileView(bg) => create_tile_view(bg, &debugger.gba),
|
||||
// TileView(bg) => create_tile_view(bg, &debugger.gba),
|
||||
Reset => {
|
||||
println!("resetting cpu...");
|
||||
debugger.gba.cpu.reset(&mut debugger.gba.sysbus);
|
||||
|
|
@ -297,13 +297,13 @@ impl Debugger {
|
|||
))),
|
||||
},
|
||||
"palette-view" => Ok(Command::PaletteView),
|
||||
"tiles" => {
|
||||
if args.len() != 1 {
|
||||
return Err(DebuggerError::InvalidCommandFormat("tile <bg>".to_string()));
|
||||
}
|
||||
let bg = self.val_number(&args[0])?;
|
||||
Ok(Command::TileView(bg))
|
||||
}
|
||||
// "tiles" => {
|
||||
// if args.len() != 1 {
|
||||
// return Err(DebuggerError::InvalidCommandFormat("tile <bg>".to_string()));
|
||||
// }
|
||||
// let bg = self.val_number(&args[0])?;
|
||||
// Ok(Command::TileView(bg))
|
||||
// }
|
||||
"bl" => Ok(Command::ListBreakpoints),
|
||||
"q" | "quit" => Ok(Command::Quit),
|
||||
"r" | "reset" => Ok(Command::Reset),
|
||||
|
|
|
|||
|
|
@ -1,107 +1,107 @@
|
|||
use std::time::Duration;
|
||||
// use std::time::Duration;
|
||||
|
||||
use sdl2::event::Event;
|
||||
use sdl2::pixels::Color;
|
||||
use sdl2::rect::{Point, Rect};
|
||||
use sdl2::render::Canvas;
|
||||
// use sdl2::event::Event;
|
||||
// use sdl2::pixels::Color;
|
||||
// use sdl2::rect::{Point, Rect};
|
||||
// use sdl2::render::Canvas;
|
||||
|
||||
use crate::core::gba::GameBoyAdvance;
|
||||
use crate::core::gpu::PixelFormat;
|
||||
// use crate::core::gba::GameBoyAdvance;
|
||||
// use crate::core::gpu::PixelFormat;
|
||||
|
||||
fn draw_tile(
|
||||
gba: &GameBoyAdvance,
|
||||
tile_addr: u32,
|
||||
pixel_format: PixelFormat,
|
||||
p: Point,
|
||||
canvas: &mut Canvas<sdl2::video::Window>,
|
||||
) {
|
||||
let io = gba.io.borrow();
|
||||
for y in 0..8 {
|
||||
for x in 0..8 {
|
||||
let index = io
|
||||
.gpu
|
||||
.read_pixel_index(&gba.sysbus, tile_addr, x, y, pixel_format);
|
||||
let color = io.gpu.get_palette_color(&gba.sysbus, index as u32, 0, 0);
|
||||
canvas.set_draw_color(Color::RGB(
|
||||
(color.r() as u8) << 3,
|
||||
(color.g() as u8) << 3,
|
||||
(color.b() as u8) << 3,
|
||||
));
|
||||
canvas.draw_point(p.offset(x as i32, y as i32)).unwrap();
|
||||
}
|
||||
}
|
||||
}
|
||||
// fn draw_tile(
|
||||
// gba: &GameBoyAdvance,
|
||||
// tile_addr: u32,
|
||||
// pixel_format: PixelFormat,
|
||||
// p: Point,
|
||||
// canvas: &mut Canvas<sdl2::video::Window>,
|
||||
// ) {
|
||||
// let io = &mut gba.sysbus.io;
|
||||
// for y in 0..8 {
|
||||
// for x in 0..8 {
|
||||
// let index = io
|
||||
// .gpu
|
||||
// .read_pixel_index(&gba.sysbus, tile_addr, x, y, pixel_format);
|
||||
// let color = io.gpu.get_palette_color(&gba.sysbus, index as u32, 0, 0);
|
||||
// canvas.set_draw_color(Color::RGB(
|
||||
// (color.r() as u8) << 3,
|
||||
// (color.g() as u8) << 3,
|
||||
// (color.b() as u8) << 3,
|
||||
// ));
|
||||
// canvas.draw_point(p.offset(x as i32, y as i32)).unwrap();
|
||||
// }
|
||||
// }
|
||||
// }
|
||||
|
||||
const TILESET_INITIAL_X: i32 = 0x20;
|
||||
const TILESET_INITIAL_Y: i32 = 0x20;
|
||||
// const TILESET_INITIAL_X: i32 = 0x20;
|
||||
// const TILESET_INITIAL_Y: i32 = 0x20;
|
||||
|
||||
pub fn create_tile_view(bg: u32, gba: &GameBoyAdvance) {
|
||||
let sdl_context = sdl2::init().unwrap();
|
||||
let video_subsystem = sdl_context.video().unwrap();
|
||||
// pub fn create_tile_view(bg: u32, gba: &GameBoyAdvance) {
|
||||
// let sdl_context = sdl2::init().unwrap();
|
||||
// let video_subsystem = sdl_context.video().unwrap();
|
||||
|
||||
let window = video_subsystem
|
||||
.window("PaletteView", 512, 512)
|
||||
.position_centered()
|
||||
.build()
|
||||
.unwrap();
|
||||
// let window = video_subsystem
|
||||
// .window("PaletteView", 512, 512)
|
||||
// .position_centered()
|
||||
// .build()
|
||||
// .unwrap();
|
||||
|
||||
let mut canvas = window.into_canvas().build().unwrap();
|
||||
// let mut canvas = window.into_canvas().build().unwrap();
|
||||
|
||||
let bgcnt = gba.io.borrow().gpu.bg[bg as usize].bgcnt.clone();
|
||||
// let bgcnt = gba.sysbus.io.gpu.bg[bg as usize].bgcnt.clone();
|
||||
|
||||
let (tile_size, pixel_format) = bgcnt.tile_format();
|
||||
let tileset_addr = bgcnt.char_block();
|
||||
let tilemap_addr = bgcnt.screen_block();
|
||||
let tiles_per_row = 32;
|
||||
let num_tiles = 0x4000 / tile_size;
|
||||
println!("tileset: {:#x}, tilemap: {:#x}", tileset_addr, tilemap_addr);
|
||||
// let (tile_size, pixel_format) = bgcnt.tile_format();
|
||||
// let tileset_addr = bgcnt.char_block();
|
||||
// let tilemap_addr = bgcnt.screen_block();
|
||||
// let tiles_per_row = 32;
|
||||
// let num_tiles = 0x4000 / tile_size;
|
||||
// println!("tileset: {:#x}, tilemap: {:#x}", tileset_addr, tilemap_addr);
|
||||
|
||||
let mut event_pump = sdl_context.event_pump().unwrap();
|
||||
'running: loop {
|
||||
for event in event_pump.poll_iter() {
|
||||
match event {
|
||||
Event::Quit { .. } => break 'running,
|
||||
Event::MouseButtonDown { x, y, .. } => {
|
||||
let click_point = Point::new(x, y);
|
||||
let mut tile_x = TILESET_INITIAL_X;
|
||||
let mut tile_y = TILESET_INITIAL_Y;
|
||||
for t in 0..num_tiles {
|
||||
let tile_addr = tileset_addr + t * tile_size;
|
||||
if t != 0 && t % tiles_per_row == 0 {
|
||||
tile_y += 10;
|
||||
tile_x = TILESET_INITIAL_Y;
|
||||
}
|
||||
tile_x += 10;
|
||||
if Rect::new(tile_x, tile_y, 8, 8).contains_point(click_point) {
|
||||
println!("tile #{:#x}, addr={:#x}", t, tile_addr);
|
||||
}
|
||||
}
|
||||
}
|
||||
_ => {}
|
||||
}
|
||||
}
|
||||
// let mut event_pump = sdl_context.event_pump().unwrap();
|
||||
// 'running: loop {
|
||||
// for event in event_pump.poll_iter() {
|
||||
// match event {
|
||||
// Event::Quit { .. } => break 'running,
|
||||
// Event::MouseButtonDown { x, y, .. } => {
|
||||
// let click_point = Point::new(x, y);
|
||||
// let mut tile_x = TILESET_INITIAL_X;
|
||||
// let mut tile_y = TILESET_INITIAL_Y;
|
||||
// for t in 0..num_tiles {
|
||||
// let tile_addr = tileset_addr + t * tile_size;
|
||||
// if t != 0 && t % tiles_per_row == 0 {
|
||||
// tile_y += 10;
|
||||
// tile_x = TILESET_INITIAL_Y;
|
||||
// }
|
||||
// tile_x += 10;
|
||||
// if Rect::new(tile_x, tile_y, 8, 8).contains_point(click_point) {
|
||||
// println!("tile #{:#x}, addr={:#x}", t, tile_addr);
|
||||
// }
|
||||
// }
|
||||
// }
|
||||
// _ => {}
|
||||
// }
|
||||
// }
|
||||
|
||||
canvas.set_draw_color(Color::RGB(00, 00, 00));
|
||||
canvas.clear();
|
||||
// canvas.set_draw_color(Color::RGB(00, 00, 00));
|
||||
// canvas.clear();
|
||||
|
||||
let mut tile_x = TILESET_INITIAL_X;
|
||||
let mut tile_y = TILESET_INITIAL_Y;
|
||||
for t in 0..num_tiles {
|
||||
let tile_addr = tileset_addr + t * tile_size;
|
||||
if t != 0 && t % tiles_per_row == 0 {
|
||||
tile_y += 10;
|
||||
tile_x = TILESET_INITIAL_Y;
|
||||
}
|
||||
tile_x += 10;
|
||||
draw_tile(
|
||||
gba,
|
||||
tile_addr,
|
||||
pixel_format,
|
||||
Point::from((tile_x, tile_y)),
|
||||
&mut canvas,
|
||||
);
|
||||
}
|
||||
canvas.present();
|
||||
::std::thread::sleep(Duration::new(0, 1_000_000_000u32 / 60));
|
||||
}
|
||||
}
|
||||
// let mut tile_x = TILESET_INITIAL_X;
|
||||
// let mut tile_y = TILESET_INITIAL_Y;
|
||||
// for t in 0..num_tiles {
|
||||
// let tile_addr = tileset_addr + t * tile_size;
|
||||
// if t != 0 && t % tiles_per_row == 0 {
|
||||
// tile_y += 10;
|
||||
// tile_x = TILESET_INITIAL_Y;
|
||||
// }
|
||||
// tile_x += 10;
|
||||
// draw_tile(
|
||||
// gba,
|
||||
// tile_addr,
|
||||
// pixel_format,
|
||||
// Point::from((tile_x, tile_y)),
|
||||
// &mut canvas,
|
||||
// );
|
||||
// }
|
||||
// canvas.present();
|
||||
// ::std::thread::sleep(Duration::new(0, 1_000_000_000u32 / 60));
|
||||
// }
|
||||
// }
|
||||
|
|
|
|||
Reference in a new issue