From cb36db688e88eec798cf600c9e77717905e1fd5c Mon Sep 17 00:00:00 2001 From: Michel Heily Date: Fri, 20 Dec 2019 15:06:21 +0200 Subject: [PATCH] Fix LSR#0 Former-commit-id: 7cfcc0b8f6e0849c9090148f2cc381b3419abd39 --- src/core/arm7tdmi/alu.rs | 31 +++++++++++++++++-------------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/src/core/arm7tdmi/alu.rs b/src/core/arm7tdmi/alu.rs index 5e45294..67d7e13 100644 --- a/src/core/arm7tdmi/alu.rs +++ b/src/core/arm7tdmi/alu.rs @@ -122,21 +122,24 @@ impl Core { } } - pub fn lsr(&mut self, val: u32, amount: u32, _carry_in: bool, immediate: bool) -> u32 { - let amount = if immediate && amount == 0 { 32 } else { amount }; - match amount { - 32 => { - self.bs_carry_out = val.bit(31); - 0 - } - 1..=31 => { - self.bs_carry_out = val >> (amount - 1) & 1 == 1; - (val as u32) >> amount - } - _ => { - self.bs_carry_out = false; - 0 + pub fn lsr(&mut self, val: u32, amount: u32, carry_in: bool, immediate: bool) -> u32 { + if amount != 0 { + match amount { + x if x < 32 => { + self.bs_carry_out = (val >> (amount - 1) & 1) == 1; + val >> amount + } + _ => { + self.bs_carry_out = false; + 0 + } } + } else if immediate { + self.bs_carry_out = val.bit(31); + 0 + } else { + self.bs_carry_out = carry_in; + val } }