timers: Fix wrong irq number

Timers were triggering DMA interrupts, wonder why.. >< Former-commit-id: 4fd2781a4bf71d0c0ebc1badae003d76a781ee75
2019-12-28 16:00:54 +02:00 · 2019-12-28 16:00:54 +02:00 · cc4f328691
parent d8545dd8cd
commit cc4f328691
1 changed files with 1 additions and 1 deletions
--- a/src/core/timer.rs
+++ b/src/core/timer.rs
@ -25,7 +25,7 @@ impl Timer {
        }
        Timer {
            timer_id: timer_id,
-            irq: Interrupt::from_usize(timer_id + 8).unwrap(),
+            irq: Interrupt::from_usize(timer_id + 3).unwrap(),
            data: 0,
            ctl: TimerCtl(0),
            initial_data: 0,