Add WAITCNT, and refactor cycle calculation
Former-commit-id: e1ee5c9ce1f1db549fddd80907467da51e63b676
This commit is contained in:
parent
fe071bf1ec
commit
d86cc87c79
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@ -1,51 +1,5 @@
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use std::fmt;
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use std::ops::Add;
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use super::Addr;
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#[derive(Debug)]
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pub enum MemoryAccessType {
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NonSeq,
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Seq,
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}
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impl fmt::Display for MemoryAccessType {
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fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
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write!(
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f,
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"{}",
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match self {
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MemoryAccessType::NonSeq => "N",
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MemoryAccessType::Seq => "S",
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}
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)
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}
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}
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#[derive(Debug)]
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pub enum MemoryAccessWidth {
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MemoryAccess8,
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MemoryAccess16,
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MemoryAccess32,
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}
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impl Add<MemoryAccessWidth> for MemoryAccessType {
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type Output = MemoryAccess;
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fn add(self, other: MemoryAccessWidth) -> Self::Output {
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MemoryAccess(self, other)
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}
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}
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#[derive(Debug)]
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pub struct MemoryAccess(pub MemoryAccessType, pub MemoryAccessWidth);
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impl fmt::Display for MemoryAccess {
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fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
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write!(f, "{}-Cycle ({:?})", self.0, self.1)
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}
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}
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pub trait Bus {
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fn read_32(&self, addr: Addr) -> u32;
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fn read_16(&self, addr: Addr) -> u16;
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@ -54,9 +8,6 @@ pub trait Bus {
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fn write_16(&mut self, addr: Addr, value: u16);
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fn write_8(&mut self, addr: Addr, value: u8);
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/// returns the number of cycles needed for this memory access
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fn get_cycles(&self, addr: Addr, access: MemoryAccess) -> usize;
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fn get_bytes(&self, range: std::ops::Range<u32>) -> Vec<u8> {
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let mut bytes = Vec::new();
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for b in range {
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@ -2,11 +2,8 @@ use std::str::from_utf8;
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use byteorder::{LittleEndian, ReadBytesExt, WriteBytesExt};
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use super::arm7tdmi::{
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bus::{Bus, MemoryAccess, MemoryAccessWidth},
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Addr,
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};
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use super::sysbus::WaitState;
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use super::arm7tdmi::{bus::Bus, Addr};
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use crate::util::read_bin_file;
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/// From GBATEK
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@ -72,7 +69,6 @@ impl CartridgeHeader {
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pub struct Cartridge {
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pub header: CartridgeHeader,
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bytes: Box<[u8]>,
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ws: WaitState,
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}
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impl Cartridge {
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@ -88,7 +84,6 @@ impl Cartridge {
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Ok(Cartridge {
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header: header,
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bytes: rom_bin.into_boxed_slice(),
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ws: WaitState::new(5, 5, 8),
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})
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}
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}
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@ -125,12 +120,4 @@ impl Bus for Cartridge {
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fn write_8(&mut self, addr: Addr, value: u8) {
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(&mut self.bytes[addr as usize..]).write_u8(value).unwrap()
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}
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fn get_cycles(&self, _addr: Addr, access: MemoryAccess) -> usize {
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match access.1 {
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MemoryAccessWidth::MemoryAccess8 => self.ws.access8,
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MemoryAccessWidth::MemoryAccess16 => self.ws.access16,
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MemoryAccessWidth::MemoryAccess32 => self.ws.access32,
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}
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}
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}
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@ -1,8 +1,9 @@
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use std::cell::RefCell;
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use std::rc::Rc;
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use super::arm7tdmi::{Addr, Bus, MemoryAccess};
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use super::arm7tdmi::{Addr, Bus};
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use super::gba::IoDevices;
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use super::sysbus::BoxedMemory;
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use super::keypad;
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pub mod consts {
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@ -124,17 +125,21 @@ use consts::*;
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#[derive(Debug)]
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pub struct IoRegs {
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mem: BoxedMemory,
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pub io: Rc<RefCell<IoDevices>>,
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pub keyinput: u16,
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pub post_boot_flag: bool,
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pub waitcnt: WaitControl, // TODO also implement 4000800
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}
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impl IoRegs {
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pub fn new(io: Rc<RefCell<IoDevices>>) -> IoRegs {
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IoRegs {
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mem: BoxedMemory::new(vec![0; 0x400].into_boxed_slice(), 0x3ff),
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io: io,
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post_boot_flag: false,
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keyinput: keypad::KEYINPUT_ALL_RELEASED,
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waitcnt: WaitControl(0),
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}
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}
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}
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@ -178,12 +183,13 @@ impl Bus for IoRegs {
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REG_TM3CNT_L => io.timers[3].timer_data,
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REG_TM3CNT_H => io.timers[3].timer_ctl.0,
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REG_WAITCNT => self.waitcnt.0,
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REG_POSTFLG => self.post_boot_flag as u16,
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REG_HALTCNT => 0,
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REG_KEYINPUT => self.keyinput as u16,
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_ => {
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println!("tried to read register {:#x}", addr + IO_BASE);
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0
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self.mem.read_16(addr)
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}
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}
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}
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@ -253,10 +259,12 @@ impl Bus for IoRegs {
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}
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REG_TM3CNT_H => io.timers[3].timer_ctl.0 = value,
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REG_WAITCNT => self.waitcnt.0 = value,
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REG_POSTFLG => self.post_boot_flag = value != 0,
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REG_HALTCNT => {}
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_ => {
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println!("tried to write register {:#x}", addr + IO_BASE);
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self.mem.write_16(addr, value);
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}
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}
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}
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@ -265,9 +273,21 @@ impl Bus for IoRegs {
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let t = self.read_16(addr);
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self.write_16(addr, (t & 0xff) | ((value as u16) << 8));
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}
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/// returns the number of cycles needed for this memory access
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fn get_cycles(&self, _addr: Addr, _access: MemoryAccess) -> usize {
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1
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}
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}
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bitfield! {
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#[derive(Default, Copy, Clone, PartialEq)]
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pub struct WaitControl(u16);
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impl Debug;
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u16;
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sram_wait_control, _: 1, 0;
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pub ws0_first_access, _: 3, 2;
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pub ws0_second_access, _: 4, 4;
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pub ws1_first_access, _: 6, 5;
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pub ws1_second_access, _: 7, 7;
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pub ws2_first_access, _: 9, 8;
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pub ws2_second_access, _: 10, 10;
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#[allow(non_snake_case)]
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PHI_terminal_output, _: 12, 11;
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prefetch, _: 14;
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}
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@ -1,11 +1,14 @@
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use std::cell::RefCell;
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use std::fmt;
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use std::ops::Add;
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use std::rc::Rc;
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use byteorder::{LittleEndian, ReadBytesExt, WriteBytesExt};
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use super::arm7tdmi::bus::{Bus, MemoryAccess, MemoryAccessWidth};
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use super::arm7tdmi::bus::Bus;
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use super::arm7tdmi::Addr;
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use super::gba::IoDevices;
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use super::gpu::GpuState;
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use super::{cartridge::Cartridge, ioregs::IoRegs};
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const VIDEO_RAM_SIZE: usize = 128 * 1024;
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@ -14,10 +17,63 @@ const INTERNAL_RAM_SIZE: usize = 32 * 1024;
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const PALETTE_RAM_SIZE: usize = 1 * 1024;
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const OAM_SIZE: usize = 1 * 1024;
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pub const BIOS_ADDR: u32 = 0x0000_0000;
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pub const EWRAM_ADDR: u32 = 0x0200_0000;
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pub const IWRAM_ADDR: u32 = 0x0300_0000;
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pub const IOMEM_ADDR: u32 = 0x0400_0000;
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pub const PALRAM_ADDR: u32 = 0x0500_0000;
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pub const VRAM_ADDR: u32 = 0x0600_0000;
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pub const OAM_ADDR: u32 = 0x0700_0000;
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pub const GAMEPAK_WS0_ADDR: u32 = 0x0800_0000;
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pub const GAMEPAK_WS1_ADDR: u32 = 0x0A00_0000;
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pub const GAMEPAK_WS2_ADDR: u32 = 0x0C00_0000;
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#[derive(Debug, Copy, Clone)]
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pub enum MemoryAccessType {
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NonSeq,
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Seq,
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}
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impl fmt::Display for MemoryAccessType {
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fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
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write!(
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f,
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"{}",
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match self {
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MemoryAccessType::NonSeq => "N",
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MemoryAccessType::Seq => "S",
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}
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)
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}
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}
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#[derive(Debug, PartialEq, Copy, Clone)]
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pub enum MemoryAccessWidth {
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MemoryAccess8,
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MemoryAccess16,
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MemoryAccess32,
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}
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impl Add<MemoryAccessWidth> for MemoryAccessType {
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type Output = MemoryAccess;
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fn add(self, other: MemoryAccessWidth) -> Self::Output {
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MemoryAccess(self, other)
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}
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}
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#[derive(Debug, Copy, Clone)]
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pub struct MemoryAccess(pub MemoryAccessType, pub MemoryAccessWidth);
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impl fmt::Display for MemoryAccess {
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fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
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write!(f, "{}-Cycle ({:?})", self.0, self.1)
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}
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}
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#[derive(Debug)]
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pub struct BoxedMemory {
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pub mem: Box<[u8]>,
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ws: WaitState,
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mask: u32,
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}
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@ -26,40 +82,8 @@ impl BoxedMemory {
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BoxedMemory {
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mem: boxed_slice,
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mask: mask,
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ws: WaitState::default(),
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}
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}
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pub fn new_with_waitstate(boxed_slice: Box<[u8]>, mask: u32, ws: WaitState) -> BoxedMemory {
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BoxedMemory {
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mem: boxed_slice,
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mask: mask,
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ws: ws,
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}
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}
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}
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#[derive(Debug)]
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pub struct WaitState {
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pub access8: usize,
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pub access16: usize,
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pub access32: usize,
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}
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impl WaitState {
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pub fn new(access8: usize, access16: usize, access32: usize) -> WaitState {
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WaitState {
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access8,
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access16,
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access32,
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}
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}
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}
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impl Default for WaitState {
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fn default() -> WaitState {
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WaitState::new(1, 1, 1)
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}
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}
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impl Bus for BoxedMemory {
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@ -96,14 +120,6 @@ impl Bus for BoxedMemory {
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.write_u8(value)
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.unwrap()
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}
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fn get_cycles(&self, _addr: Addr, access: MemoryAccess) -> usize {
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match access.1 {
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MemoryAccessWidth::MemoryAccess8 => self.ws.access8,
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MemoryAccessWidth::MemoryAccess16 => self.ws.access16,
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MemoryAccessWidth::MemoryAccess32 => self.ws.access32,
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}
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}
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}
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#[derive(Debug)]
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@ -127,10 +143,6 @@ impl Bus for DummyBus {
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fn write_16(&mut self, _addr: Addr, _value: u16) {}
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fn write_8(&mut self, _addr: Addr, _value: u8) {}
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fn get_cycles(&self, _addr: Addr, _access: MemoryAccess) -> usize {
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1
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}
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}
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#[derive(Debug)]
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@ -160,25 +172,22 @@ impl SysBus {
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io: io,
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bios: BoxedMemory::new(bios_rom.into_boxed_slice(), 0xff_ffff),
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onboard_work_ram: BoxedMemory::new_with_waitstate(
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onboard_work_ram: BoxedMemory::new(
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vec![0; WORK_RAM_SIZE].into_boxed_slice(),
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(WORK_RAM_SIZE as u32) - 1,
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WaitState::new(3, 3, 6),
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),
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internal_work_ram: BoxedMemory::new(
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vec![0; INTERNAL_RAM_SIZE].into_boxed_slice(),
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0x7fff,
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),
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ioregs: ioregs,
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palette_ram: BoxedMemory::new_with_waitstate(
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palette_ram: BoxedMemory::new(
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vec![0; PALETTE_RAM_SIZE].into_boxed_slice(),
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(PALETTE_RAM_SIZE as u32) - 1,
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WaitState::new(1, 1, 2),
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),
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vram: BoxedMemory::new_with_waitstate(
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vram: BoxedMemory::new(
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vec![0; VIDEO_RAM_SIZE].into_boxed_slice(),
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(VIDEO_RAM_SIZE as u32) - 1,
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WaitState::new(1, 1, 2),
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),
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oam: BoxedMemory::new(vec![0; OAM_SIZE].into_boxed_slice(), (OAM_SIZE as u32) - 1),
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gamepak: gamepak,
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@ -187,33 +196,86 @@ impl SysBus {
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}
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fn map(&self, addr: Addr) -> &Bus {
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match (addr & 0xff000000) as usize {
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0x00000000 => &self.bios,
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0x02000000 => &self.onboard_work_ram,
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0x03000000 => &self.internal_work_ram,
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0x04000000 => &self.ioregs,
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0x05000000 => &self.palette_ram,
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0x06000000 => &self.vram,
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0x07000000 => &self.oam,
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0x08000000 => &self.gamepak,
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match addr & 0xff000000 {
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BIOS_ADDR => &self.bios,
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EWRAM_ADDR => &self.onboard_work_ram,
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IWRAM_ADDR => &self.internal_work_ram,
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IOMEM_ADDR => &self.ioregs,
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PALRAM_ADDR => &self.palette_ram,
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VRAM_ADDR => &self.vram,
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OAM_ADDR => &self.oam,
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GAMEPAK_WS0_ADDR | GAMEPAK_WS1_ADDR | GAMEPAK_WS2_ADDR => &self.gamepak,
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_ => &self.dummy,
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}
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}
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/// TODO proc-macro for generating this function
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fn map_mut(&mut self, addr: Addr) -> &mut Bus {
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match (addr & 0xff000000) as usize {
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0x00000000 => &mut self.bios,
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0x02000000 => &mut self.onboard_work_ram,
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0x03000000 => &mut self.internal_work_ram,
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0x04000000 => &mut self.ioregs,
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0x05000000 => &mut self.palette_ram,
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0x06000000 => &mut self.vram,
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0x07000000 => &mut self.oam,
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0x08000000 => &mut self.gamepak,
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match addr & 0xff000000 {
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BIOS_ADDR => &mut self.bios,
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EWRAM_ADDR => &mut self.onboard_work_ram,
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IWRAM_ADDR => &mut self.internal_work_ram,
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IOMEM_ADDR => &mut self.ioregs,
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PALRAM_ADDR => &mut self.palette_ram,
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VRAM_ADDR => &mut self.vram,
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OAM_ADDR => &mut self.oam,
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GAMEPAK_WS0_ADDR | GAMEPAK_WS1_ADDR | GAMEPAK_WS2_ADDR => &mut self.gamepak,
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_ => &mut self.dummy,
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}
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}
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pub fn get_cycles(&self, addr: Addr, access: MemoryAccess) -> usize {
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let nonseq_cycles = [4, 3, 2, 8];
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let seq_cycles = [2, 1];
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let mut cycles = 0;
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// TODO handle EWRAM accesses
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match addr & 0xff000000 {
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EWRAM_ADDR => {
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match access.1 {
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MemoryAccessWidth::MemoryAccess32 => cycles += 6,
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_ => cycles += 3
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}
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}
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OAM_ADDR | VRAM_ADDR | PALRAM_ADDR => {
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match access.1 {
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MemoryAccessWidth::MemoryAccess32 => cycles += 2,
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_ => cycles += 1
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}
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if self.io.borrow().gpu.state == GpuState::HDraw {
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cycles += 1;
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}
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}
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GAMEPAK_WS0_ADDR => {
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match access.0 {
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MemoryAccessType::NonSeq => {
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match access.1 {
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MemoryAccessWidth::MemoryAccess32 => {
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cycles += nonseq_cycles[self.ioregs.waitcnt.ws0_first_access() as usize];
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cycles += seq_cycles[self.ioregs.waitcnt.ws0_second_access() as usize];
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}
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_ => {
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cycles += nonseq_cycles[self.ioregs.waitcnt.ws0_first_access() as usize];
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}
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}
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}
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MemoryAccessType::Seq => {
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cycles += seq_cycles[self.ioregs.waitcnt.ws0_second_access() as usize];
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if access.1 == MemoryAccessWidth::MemoryAccess32 {
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cycles += seq_cycles[self.ioregs.waitcnt.ws0_second_access() as usize];
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}
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}
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}
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},
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GAMEPAK_WS1_ADDR | GAMEPAK_WS2_ADDR => {
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panic!("unimplemented - need to refactor code with a nice macro :(")
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}
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_ => {}
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}
|
||||
|
||||
cycles
|
||||
}
|
||||
}
|
||||
|
||||
impl Bus for SysBus {
|
||||
|
@ -240,8 +302,4 @@ impl Bus for SysBus {
|
|||
fn write_8(&mut self, addr: Addr, value: u8) {
|
||||
self.map_mut(addr).write_8(addr & 0xff_ffff, value)
|
||||
}
|
||||
|
||||
fn get_cycles(&self, addr: Addr, access: MemoryAccess) -> usize {
|
||||
self.map(addr).get_cycles(addr & 0xff_ffff, access)
|
||||
}
|
||||
}
|
||||
|
|
Reference in a new issue