From e06c77b6fd212b88e1ff21a0d381f04ec5409f05 Mon Sep 17 00:00:00 2001
From: Michel Heily <michelheily@gmail.com>
Date: Sat, 27 Jul 2019 18:56:34 +0300
Subject: [PATCH] armwrestler-fix: Fix MULL_MLAL instructions

Also fix disassembly for MULL_MLAL


Former-commit-id: f535b2db7edb5d056160699436dbeb0c15e61388
---
 src/core/arm7tdmi/arm/display.rs | 36 +++++++++++---------------------
 src/core/arm7tdmi/arm/exec.rs    | 16 +++++++-------
 2 files changed, 21 insertions(+), 31 deletions(-)

diff --git a/src/core/arm7tdmi/arm/display.rs b/src/core/arm7tdmi/arm/display.rs
index f6dccb7..2c36da5 100644
--- a/src/core/arm7tdmi/arm/display.rs
+++ b/src/core/arm7tdmi/arm/display.rs
@@ -352,30 +352,18 @@ impl ArmInstruction {
     }
 
     fn fmt_mull_mlal(&self, f: &mut fmt::Formatter) -> fmt::Result {
-        if self.accumulate_flag() {
-            write!(
-                f,
-                "{sign}mlal{S}{cond}\t{RdLo}, {RdHi}, {Rm}, {Rs}",
-                sign = self.sign_mark(),
-                S = self.set_cond_mark(),
-                cond = self.cond,
-                RdLo = reg_string(self.rd_lo()),
-                RdHi = reg_string(self.rd_hi()),
-                Rm = reg_string(self.rm()),
-                Rs = reg_string(self.rs()),
-            )
-        } else {
-            write!(
-                f,
-                "{sign}mull{S}{cond}\t{RdLo}, {RdHi}, {Rm}",
-                sign = self.sign_mark(),
-                S = self.set_cond_mark(),
-                cond = self.cond,
-                RdLo = reg_string(self.rd_lo()),
-                RdHi = reg_string(self.rd_hi()),
-                Rm = reg_string(self.rm())
-            )
-        }
+        write!(
+            f,
+            "{sign}{mnem}{S}{cond}\t{RdLo}, {RdHi}, {Rm}, {Rs}",
+            sign = self.sign_mark(),
+            mnem = if self.accumulate_flag() { "mlal" } else { "mull" },
+            S = self.set_cond_mark(),
+            cond = self.cond,
+            RdLo = reg_string(self.rd_lo()),
+            RdHi = reg_string(self.rd_hi()),
+            Rm = reg_string(self.rm()),
+            Rs = reg_string(self.rs()),
+        )
     }
 
     fn fmt_ldr_str_hs(&self, f: &mut fmt::Formatter) -> fmt::Result {
diff --git a/src/core/arm7tdmi/arm/exec.rs b/src/core/arm7tdmi/arm/exec.rs
index 30d1009..25b9891 100644
--- a/src/core/arm7tdmi/arm/exec.rs
+++ b/src/core/arm7tdmi/arm/exec.rs
@@ -464,13 +464,13 @@ impl Core {
             return Err(CpuError::IllegalInstruction);
         }
 
-        let op1 = self.get_reg(rm) as u64;
-        let op2 = self.get_reg(rs) as u64;
+        let op1 = self.get_reg(rm);
+        let op2 = self.get_reg(rs);
         let mut result: u64 = if insn.u_flag() {
             // signed
-            (op1 as i64).wrapping_mul(op2 as i64) as u64
+            (op1 as i32 as i64).wrapping_mul(op2 as i32 as i64) as u64
         } else {
-            op1.wrapping_mul(op2)
+            (op1 as u64).wrapping_mul(op2 as u64)
         };
         self.add_cycle();
 
@@ -481,8 +481,8 @@ impl Core {
             self.add_cycle();
         }
 
-        self.set_reg(rd_hi, (result >> 32) as u32);
-        self.set_reg(rd_lo, (result & 0xffffffff) as u32);
+        self.set_reg(rd_hi, (result >> 32) as i32 as u32);
+        self.set_reg(rd_lo, (result & 0xffffffff) as i32 as u32);
 
         let m = self.get_required_multipiler_array_cycles(self.get_reg(rs) as i32);
         for _ in 0..m {
@@ -490,8 +490,10 @@ impl Core {
         }
 
         if insn.set_cond_flag() {
-            self.cpsr.set_N((result as i64) < 0);
+            self.cpsr.set_N(result.bit(63));
             self.cpsr.set_Z(result == 0);
+            self.cpsr.set_C(false);
+            self.cpsr.set_V(false);
         }
 
         Ok(())