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Fix LR again :(

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Former-commit-id: 820315154ae58dcc29c4a8921094598f149b0255
This commit is contained in:
Michel Heily 2019-07-05 03:27:23 +03:00
parent 2293300260
commit e66a8a9a3b
1 changed files with 5 additions and 3 deletions
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8
src/arm7tdmi/cpu.rs
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@ -131,11 +131,10 @@ impl Core {
let curr_index = curr_mode.bank_index(); let curr_index = curr_mode.bank_index();
self.gpr_banked_r13[curr_index] = self.gpr[13]; self.gpr_banked_r13[curr_index] = self.gpr[13];
self.gpr[13] = self.gpr_banked_r13[next_index];
self.gpr_banked_r14[curr_index] = self.gpr[14]; self.gpr_banked_r14[curr_index] = self.gpr[14];
self.gpr[13] = self.gpr_banked_r13[next_index];
self.gpr[14] = self.gpr_banked_r14[next_index]; self.gpr[14] = self.gpr_banked_r14[next_index];
self.gpr_banked_r14[next_index] = self.get_next_pc(); // Store the return address in LR_mode
if new_mode == CpuMode::Fiq { if new_mode == CpuMode::Fiq {
for r in 0..5 { for r in 0..5 {
@ -157,6 +156,9 @@ impl Core {
self.spsr[index] = self.cpsr; self.spsr[index] = self.cpsr;
} }
self.map_banked_registers(curr_mode, new_mode); self.map_banked_registers(curr_mode, new_mode);
let next_index = new_mode.bank_index();
self.gpr_banked_r14[next_index] = self.pc.wrapping_sub(self.word_size() as u32).wrapping_add(4);
} }
/// Resets the cpu /// Resets the cpu