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core: Fix 8bit accesses to mgba log

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Former-commit-id: 780e6b58b265ad5d586fe605f143e6c9d8b26c63
Former-commit-id: 5d2514c9a45d2f5c698272c9324575d7bddec4ac
This commit is contained in:
Michel Heily 2020-10-24 09:32:43 -07:00 committed by MishMish
parent fb32b9a671
commit efb1cdb4b6
1 changed files with 17 additions and 11 deletions
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28
core/src/mgba_debug.rs
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@ -4,7 +4,9 @@ use std::str;
use log::log; use log::log;
use log::Level; use log::Level;
use super::bus::Bus;
use super::iodev::consts::{REG_DEBUG_ENABLE, REG_DEBUG_FLAGS, REG_DEBUG_STRING}; use super::iodev::consts::{REG_DEBUG_ENABLE, REG_DEBUG_FLAGS, REG_DEBUG_STRING};
pub const DEBUG_STRING_SIZE: usize = 0x100; pub const DEBUG_STRING_SIZE: usize = 0x100;
#[derive(Clone, Serialize, Deserialize)] #[derive(Clone, Serialize, Deserialize)]
@ -30,14 +32,15 @@ impl DebugPort {
|| (x >= REG_DEBUG_STRING && x <= REG_DEBUG_STRING + (DEBUG_STRING_SIZE as u32)) || (x >= REG_DEBUG_STRING && x <= REG_DEBUG_STRING + (DEBUG_STRING_SIZE as u32))
} }
pub fn read(&self, addr: u32) -> u16 { pub fn read(&mut self, addr: u32) -> u16 {
match addr { if !self.enable {
REG_DEBUG_ENABLE => { return 0;
if self.enable {
0x1DEA
} else {
0
} }
match addr {
REG_DEBUG_ENABLE => 0x1DEA,
REG_DEBUG_FLAGS => self.flags.0,
x if x >= REG_DEBUG_STRING && x <= REG_DEBUG_STRING + (DEBUG_STRING_SIZE as u32) => {
self.debug_string.read_16(addr - REG_DEBUG_STRING)
} }
_ => 0, _ => 0,
} }
@ -45,7 +48,10 @@ impl DebugPort {
pub fn write(&mut self, addr: u32, value: u16) { pub fn write(&mut self, addr: u32, value: u16) {
match addr { match addr {
REG_DEBUG_ENABLE => self.enable = value == 0xC0DE, REG_DEBUG_ENABLE => {
self.enable = value == 0xC0DE;
info!("mGBA log enabled: {}", self.enable);
}
REG_DEBUG_FLAGS => { REG_DEBUG_FLAGS => {
if self.enable { if self.enable {
self.flags.0 = value; self.flags.0 = value;
@ -53,9 +59,9 @@ impl DebugPort {
} }
} }
x if x >= REG_DEBUG_STRING && x <= REG_DEBUG_STRING + (DEBUG_STRING_SIZE as u32) => { x if x >= REG_DEBUG_STRING && x <= REG_DEBUG_STRING + (DEBUG_STRING_SIZE as u32) => {
let index = (addr - REG_DEBUG_STRING) as usize; if self.enable {
self.debug_string[index] = (value & 0xff) as u8; self.debug_string.write_16(addr - REG_DEBUG_STRING, value);
self.debug_string[index + 1] = (value >> 8) as u8; }
} }
_ => unreachable!(), _ => unreachable!(),
} }