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Fix thumb conditional branch offset

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Former-commit-id: b42f233b7f2ca5d427b0e36860a305f7e1a26a1d
This commit is contained in:
Michel Heily 2019-07-27 21:30:27 +03:00
parent df48f307f0
commit f39095a03b
3 changed files with 7 additions and 7 deletions
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4
src/core/arm7tdmi/thumb/display.rs
View file

@ -23,7 +23,7 @@ impl ThumbInstruction {
"{op}\t{Rd}, #{Offset8:#x}", "{op}\t{Rd}, #{Offset8:#x}",
op = self.format3_op(), op = self.format3_op(),
Rd = reg_string(self.rd()), Rd = reg_string(self.rd()),
Offset8 = self.offset8() Offset8 = self.raw & 0xff
) )
} }
@ -252,7 +252,7 @@ impl ThumbInstruction {
"b{cond}\t{addr:#x}", "b{cond}\t{addr:#x}",
cond = self.cond(), cond = self.cond(),
addr = { addr = {
let offset = ((self.offset8() as i8) << 1) as i32; let offset = self.bcond_offset();
(self.pc as i32 + 4).wrapping_add(offset) as Addr (self.pc as i32 + 4).wrapping_add(offset) as Addr
} }
) )

4
src/core/arm7tdmi/thumb/exec.rs
View file

@ -69,7 +69,7 @@ impl Core {
) -> CpuExecResult { ) -> CpuExecResult {
let arm_alu_op: AluOpCode = insn.format3_op().into(); let arm_alu_op: AluOpCode = insn.format3_op().into();
let op1 = self.get_reg(insn.rd()) as i32; let op1 = self.get_reg(insn.rd()) as i32;
let op2 = insn.offset8() as u8 as i32; let op2 = ((insn.raw & 0xff) as i8) as u8 as i32;
let result = self.alu_flags(arm_alu_op, op1, op2); let result = self.alu_flags(arm_alu_op, op1, op2);
if let Some(result) = result { if let Some(result) = result {
self.set_reg(insn.rd(), result as u32); self.set_reg(insn.rd(), result as u32);
@ -388,7 +388,7 @@ impl Core {
if !self.check_arm_cond(insn.cond()) { if !self.check_arm_cond(insn.cond()) {
Ok(()) Ok(())
} else { } else {
let offset = ((insn.offset8() as i8) << 1) as i32; let offset = insn.bcond_offset();
self.pc = (self.pc as i32).wrapping_add(offset) as u32; self.pc = (self.pc as i32).wrapping_add(offset) as u32;
self.flush_pipeline(); self.flush_pipeline();
Ok(()) Ok(())

6
src/core/arm7tdmi/thumb/mod.rs
View file

@ -294,8 +294,8 @@ impl ThumbInstruction {
self.raw.bit_range(6..11) as i8 self.raw.bit_range(6..11) as i8
} }
pub fn offset8(&self) -> i8 { pub fn bcond_offset(&self) -> i32 {
self.raw.bit_range(0..8) as i8 ((((self.raw & 0xff) as u32) << 24) as i32) >> 23
} }
pub fn offset11(&self) -> i32 { pub fn offset11(&self) -> i32 {
@ -303,7 +303,7 @@ impl ThumbInstruction {
} }
pub fn word8(&self) -> u16 { pub fn word8(&self) -> u16 {
self.raw.bit_range(0..8) << 2 (self.raw & 0xff) << 2
} }
pub fn is_transferring_bytes(&self) -> bool { pub fn is_transferring_bytes(&self) -> bool {